Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	623271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3567819

1

T5

6

T6

24

T7

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1028690	1			T5	7		T6	19		T23	8
values[0x0]	1455364	1			T5	8		T6	21		T7	10
values[0x1]	1707036	1			T5	7		T6	18		T7	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	344222	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3846868

1

T5

9

T6

25

T7

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17235	1			T23	1		T1	111		T19	1
valid_sources[0x01]	16313	1			T1	54		T19	1		T2	628
valid_sources[0x02]	16663	1			T1	113		T18	14		T2	755
valid_sources[0x03]	15974	1			T5	2		T1	101		T19	2
valid_sources[0x04]	15088	1			T23	1		T1	100		T2	93
valid_sources[0x05]	17417	1			T1	102		T19	2		T2	238
valid_sources[0x06]	16386	1			T5	1		T1	117		T2	240
valid_sources[0x07]	16864	1			T22	1		T1	76		T19	2
valid_sources[0x08]	17947	1			T6	1		T1	110		T19	3
valid_sources[0x09]	16198	1			T22	1		T1	112		T19	2
valid_sources[0x0a]	16036	1			T6	1		T23	2		T1	102
valid_sources[0x0b]	16329	1			T24	2		T1	84		T19	2
valid_sources[0x0c]	15120	1			T1	119		T19	4		T2	74
valid_sources[0x0d]	15612	1			T1	133		T19	1		T4	10
valid_sources[0x0e]	16675	1			T24	1		T1	132		T19	4
valid_sources[0x0f]	15065	1			T24	1		T1	157		T2	246
valid_sources[0x10]	15448	1			T6	1		T1	134		T19	1
valid_sources[0x11]	16240	1			T6	1		T1	115		T19	1
valid_sources[0x12]	17161	1			T23	1		T1	142		T4	2
valid_sources[0x13]	19435	1			T1	92		T19	1		T2	121
valid_sources[0x14]	15822	1			T1	158		T19	2		T2	148
valid_sources[0x15]	15872	1			T6	1		T1	80		T17	28
valid_sources[0x16]	16191	1			T1	99		T19	1		T2	52
valid_sources[0x17]	16401	1			T6	1		T1	105		T2	160
valid_sources[0x18]	16976	1			T25	1		T1	74		T19	1
valid_sources[0x19]	15780	1			T6	1		T24	3		T1	110
valid_sources[0x1a]	15094	1			T23	1		T1	122		T4	1
valid_sources[0x1b]	15495	1			T6	1		T1	137		T19	1
valid_sources[0x1c]	16720	1			T1	179		T2	593		T20	3
valid_sources[0x1d]	17839	1			T1	121		T19	8		T2	628
valid_sources[0x1e]	15428	1			T7	5		T24	4		T1	73
valid_sources[0x1f]	17272	1			T1	85		T2	36		T20	1
valid_sources[0x20]	15579	1			T1	115		T19	2		T2	62
valid_sources[0x21]	14083	1			T1	74		T19	1		T2	21
valid_sources[0x22]	18222	1			T1	132		T19	3		T2	373
valid_sources[0x23]	17371	1			T1	74		T19	1		T4	2
valid_sources[0x24]	16365	1			T1	160		T19	3		T4	5
valid_sources[0x25]	15728	1			T23	1		T1	145		T2	613
valid_sources[0x26]	16417	1			T24	1		T25	1		T1	138
valid_sources[0x27]	15645	1			T6	2		T1	106		T16	2
valid_sources[0x28]	17682	1			T1	141		T4	2		T2	380
valid_sources[0x29]	17289	1			T6	1		T1	77		T19	3
valid_sources[0x2a]	17445	1			T1	143		T4	1		T2	804
valid_sources[0x2b]	17246	1			T24	1		T1	137		T19	1
valid_sources[0x2c]	15115	1			T1	70		T2	135		T20	1
valid_sources[0x2d]	16037	1			T1	121		T19	2		T2	232
valid_sources[0x2e]	16396	1			T6	1		T1	83		T19	2
valid_sources[0x2f]	17118	1			T1	117		T19	1		T4	3
valid_sources[0x30]	16356	1			T6	1		T1	108		T19	1
valid_sources[0x31]	15228	1			T6	1		T1	87		T4	5
valid_sources[0x32]	17806	1			T25	1		T1	132		T4	3
valid_sources[0x33]	17408	1			T6	1		T1	129		T19	4
valid_sources[0x34]	16664	1			T1	106		T19	1		T4	2
valid_sources[0x35]	17222	1			T23	2		T1	120		T2	16
valid_sources[0x36]	15870	1			T6	1		T1	98		T19	1
valid_sources[0x37]	16556	1			T1	121		T19	2		T2	203
valid_sources[0x38]	16277	1			T1	106		T19	1		T4	2
valid_sources[0x39]	15420	1			T6	1		T1	90		T19	2
valid_sources[0x3a]	15915	1			T23	2		T1	97		T19	1
valid_sources[0x3b]	17090	1			T6	1		T22	1		T1	146
valid_sources[0x3c]	15793	1			T1	117		T2	723		T3	225
valid_sources[0x3d]	17523	1			T6	2		T1	85		T19	1
valid_sources[0x3e]	16968	1			T25	1		T1	58		T2	756
valid_sources[0x3f]	17585	1			T1	159		T4	9		T2	1189
valid_sources[0x40]	15656	1			T25	1		T1	130		T2	33
valid_sources[0x41]	15765	1			T1	104		T2	108		T21	1
valid_sources[0x42]	16523	1			T1	74		T2	474		T20	1
valid_sources[0x43]	15835	1			T1	149		T19	2		T4	2
valid_sources[0x44]	15999	1			T1	131		T19	2		T4	8
valid_sources[0x45]	15963	1			T1	84		T15	2		T19	1
valid_sources[0x46]	16119	1			T1	120		T19	1		T4	4
valid_sources[0x47]	15266	1			T1	100		T4	3		T2	183
valid_sources[0x48]	17285	1			T1	108		T2	456		T20	2
valid_sources[0x49]	16423	1			T1	124		T4	7		T2	403
valid_sources[0x4a]	16954	1			T1	100		T19	1		T4	3
valid_sources[0x4b]	16841	1			T1	100		T19	1		T4	1
valid_sources[0x4c]	16535	1			T5	1		T1	123		T19	2
valid_sources[0x4d]	15391	1			T25	1		T1	91		T19	1
valid_sources[0x4e]	17495	1			T1	133		T18	5		T19	2
valid_sources[0x4f]	16718	1			T1	80		T15	2		T19	3
valid_sources[0x50]	16847	1			T6	2		T23	1		T1	165
valid_sources[0x51]	15952	1			T1	73		T15	2		T4	3
valid_sources[0x52]	15363	1			T1	103		T19	4		T2	465
valid_sources[0x53]	17722	1			T1	93		T2	222		T20	2
valid_sources[0x54]	15310	1			T22	1		T1	107		T19	1
valid_sources[0x55]	17834	1			T1	80		T19	1		T2	156
valid_sources[0x56]	15936	1			T5	1		T6	1		T1	116
valid_sources[0x57]	16248	1			T6	1		T1	95		T2	237
valid_sources[0x58]	16677	1			T6	1		T24	1		T1	80
valid_sources[0x59]	16750	1			T5	2		T1	122		T19	3
valid_sources[0x5a]	15772	1			T1	103		T19	1		T2	35
valid_sources[0x5b]	16600	1			T1	104		T19	2		T2	194
valid_sources[0x5c]	15645	1			T1	79		T19	1		T4	5
valid_sources[0x5d]	15386	1			T5	1		T6	1		T1	116
valid_sources[0x5e]	16274	1			T23	1		T24	4		T1	105
valid_sources[0x5f]	16231	1			T1	113		T4	8		T2	509
valid_sources[0x60]	16794	1			T1	124		T19	3		T4	1
valid_sources[0x61]	17808	1			T1	98		T19	1		T2	775
valid_sources[0x62]	16006	1			T1	90		T2	125		T3	219
valid_sources[0x63]	17368	1			T7	1		T24	3		T1	66
valid_sources[0x64]	15223	1			T22	1		T1	79		T19	2
valid_sources[0x65]	15982	1			T1	74		T15	1		T19	2
valid_sources[0x66]	16378	1			T23	2		T1	98		T15	1
valid_sources[0x67]	15719	1			T1	77		T19	1		T4	8
valid_sources[0x68]	16460	1			T1	88		T19	3		T2	410
valid_sources[0x69]	15652	1			T6	1		T1	106		T15	1
valid_sources[0x6a]	15887	1			T6	1		T1	98		T19	2
valid_sources[0x6b]	15447	1			T1	132		T19	2		T2	244
valid_sources[0x6c]	16837	1			T1	96		T19	1		T2	347
valid_sources[0x6d]	15294	1			T1	87		T2	362		T20	5
valid_sources[0x6e]	16209	1			T6	1		T1	77		T19	1
valid_sources[0x6f]	15819	1			T1	124		T19	2		T2	196
valid_sources[0x70]	18128	1			T6	1		T25	1		T1	105
valid_sources[0x71]	15611	1			T24	2		T25	2		T1	85
valid_sources[0x72]	15631	1			T1	99		T15	1		T19	2
valid_sources[0x73]	14865	1			T1	90		T19	3		T2	556
valid_sources[0x74]	16992	1			T6	1		T1	89		T19	3
valid_sources[0x75]	16560	1			T1	147		T15	1		T2	107
valid_sources[0x76]	16948	1			T6	1		T1	88		T2	203
valid_sources[0x77]	15091	1			T1	82		T19	1		T4	4
valid_sources[0x78]	15448	1			T5	1		T1	133		T19	1
valid_sources[0x79]	17267	1			T6	1		T1	111		T19	1
valid_sources[0x7a]	18684	1			T1	111		T19	4		T4	6
valid_sources[0x7b]	15804	1			T1	133		T2	80		T20	3
valid_sources[0x7c]	15529	1			T1	95		T19	1		T2	323
valid_sources[0x7d]	15288	1			T23	1		T24	2		T1	106
valid_sources[0x7e]	15133	1			T1	144		T19	5		T4	1
valid_sources[0x7f]	16644	1			T24	1		T1	160		T19	1
valid_sources[0x80]	16339	1			T1	136		T4	6		T2	457

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

900083

1

T5

3

T6

14

T23

6

values[0x0]

all_enables

biggest_size

1359172

1

T5

3

T6

8

T7

3

values[0x1]

all_enables

biggest_size

1308564

1

T6

2

T22

1

T24

2