SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[clkmgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 11496200 | 0 | T5 | 22 | T6 | 58 | T7 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 11496022 | 1 | T5 | 22 | T6 | 58 | T7 | 11 | ||||
values[1] | 26 | 1 | T92 | 1 | T93 | 1 | T104 | 2 | ||||
values[2] | 3 | 1 | T96 | 1 | T155 | 1 | T156 | 1 | ||||
values[3] | 84 | 1 | T91 | 4 | T92 | 8 | T93 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 11496003 | 1 | T5 | 22 | T6 | 58 | T7 | 11 | ||||
values[1] | 17 | 1 | T91 | 1 | T92 | 1 | T93 | 1 | ||||
values[2] | 4 | 1 | T92 | 1 | T102 | 1 | T157 | 1 | ||||
values[3] | 98 | 1 | T91 | 5 | T92 | 10 | T93 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 11495910 | 1 | T5 | 22 | T6 | 58 | T7 | 11 | ||||
auto[TlIntgErrCmd] | 93 | 1 | T91 | 2 | T92 | 4 | T93 | 1 | ||||
auto[TlIntgErrData] | 112 | 1 | T91 | 3 | T92 | 8 | T93 | 1 | ||||
auto[TlIntgErrBoth] | 85 | 1 | T91 | 5 | T92 | 8 | T93 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |