Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	809677490	75994	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	809677490	75994	0	0
T1	642245	390	0	0
T2	1203225	1100	0	0
T3	0	642	0	0
T4	185570	0	0	0
T8	0	50	0	0
T9	0	92	0	0
T10	0	90	0	0
T11	0	306	0	0
T12	0	936	0	0
T13	0	138	0	0
T14	0	93	0	0
T15	11640	0	0	0
T16	3355	0	0	0
T17	7925	0	0	0
T18	13410	0	0	0
T19	51840	0	0	0
T20	519115	0	0	0
T21	10240	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161935498	11208	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	11208	0	0
T1	128449	55	0	0
T2	240645	213	0	0
T3	0	93	0	0
T4	37114	0	0	0
T8	0	8	0	0
T9	0	13	0	0
T10	0	11	0	0
T11	0	39	0	0
T12	0	119	0	0
T13	0	23	0	0
T14	0	16	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161935498	15260	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	15260	0	0
T1	128449	79	0	0
T2	240645	213	0	0
T3	0	128	0	0
T4	37114	0	0	0
T8	0	10	0	0
T9	0	18	0	0
T10	0	17	0	0
T11	0	61	0	0
T12	0	187	0	0
T13	0	27	0	0
T14	0	19	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161935498	23067	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	23067	0	0
T1	128449	123	0	0
T2	240645	248	0	0
T3	0	200	0	0
T4	37114	0	0	0
T8	0	14	0	0
T9	0	31	0	0
T10	0	31	0	0
T11	0	104	0	0
T12	0	307	0	0
T13	0	37	0	0
T14	0	23	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161935498	11061	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	11061	0	0
T1	128449	55	0	0
T2	240645	213	0	0
T3	0	92	0	0
T4	37114	0	0	0
T8	0	8	0	0
T9	0	12	0	0
T10	0	13	0	0
T11	0	39	0	0
T12	0	134	0	0
T13	0	23	0	0
T14	0	16	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161935498	15398	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	15398	0	0
T1	128449	78	0	0
T2	240645	213	0	0
T3	0	129	0	0
T4	37114	0	0	0
T8	0	10	0	0
T9	0	18	0	0
T10	0	18	0	0
T11	0	63	0	0
T12	0	189	0	0
T13	0	28	0	0
T14	0	19	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0