Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T18,T19

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	161935498	159405919	0	0
AllClkBypReqTrue_A	161935498	137393	0	0
IoClkBypReqFalse_A	161935498	159321654	0	2415
IoClkBypReqTrue_A	161935498	217182	0	0
LcClkBypAckFalse_A	161935498	159418312	0	0
LcClkBypAckTrue_A	161935498	125000	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	159405919	0	0
T1	128449	127770	0	0
T5	1296	1260	0	0
T6	2428	2265	0	0
T7	1005	951	0	0
T15	2328	2025	0	0
T16	671	650	0	0
T22	2652	2545	0	0
T23	1596	1376	0	0
T24	1568	1424	0	0
T25	1421	1328	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	137393	0	0
T1	128449	1070	0	0
T2	0	2321	0	0
T6	2428	37	0	0
T7	1005	0	0	0
T15	2328	118	0	0
T16	671	0	0	0
T17	1585	194	0	0
T19	0	747	0	0
T20	0	221	0	0
T22	2652	0	0	0
T23	1596	122	0	0
T24	1568	82	0	0
T25	1421	61	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	159321654	0	2415
T1	128449	127736	0	3
T5	1296	1074	0	3
T6	2428	1838	0	3
T7	1005	949	0	3
T15	2328	1807	0	3
T16	671	648	0	3
T22	2652	2543	0	3
T23	1596	1349	0	3
T24	1568	1440	0	3
T25	1421	1250	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	217182	0	0
T1	128449	1399	0	0
T2	0	3447	0	0
T5	1296	184	0	0
T6	2428	462	0	0
T7	1005	0	0	0
T15	2328	334	0	0
T16	671	0	0	0
T17	0	315	0	0
T19	0	1118	0	0
T22	2652	0	0	0
T23	1596	147	0	0
T24	1568	64	0	0
T25	1421	137	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	159418312	0	0
T1	128449	127786	0	0
T5	1296	1205	0	0
T6	2428	2057	0	0
T7	1005	951	0	0
T15	2328	1921	0	0
T16	671	650	0	0
T22	2652	2545	0	0
T23	1596	1397	0	0
T24	1568	1490	0	0
T25	1421	1348	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	125000	0	0
T1	128449	911	0	0
T2	0	2068	0	0
T5	1296	55	0	0
T6	2428	245	0	0
T7	1005	0	0	0
T15	2328	222	0	0
T16	671	0	0	0
T17	0	148	0	0
T19	0	602	0	0
T22	2652	0	0	0
T23	1596	101	0	0
T24	1568	16	0	0
T25	1421	41	0	0