Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	14826	0	0
TransStop_A	2147483647	7534	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14826	0	0
T1	1041356	141	0	0
T2	1371996	500	0	0
T3	0	326	0	0
T4	645456	0	0	0
T15	9316	0	0	0
T16	19188	0	0	0
T17	126844	0	0	0
T18	44716	7	0	0
T19	43204	8	0	0
T20	428128	34	0	0
T21	163932	33	0	0
T27	0	4	0	0
T28	0	51	0	0
T110	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7534	0	0
T1	1041356	69	0	0
T2	1371996	250	0	0
T3	0	173	0	0
T4	645456	0	0	0
T15	9316	0	0	0
T16	19188	0	0	0
T17	126844	0	0	0
T18	44716	2	0	0
T19	43204	0	0	0
T20	428128	27	0	0
T21	163932	21	0	0
T27	0	4	0	0
T28	0	27	0	0
T109	0	21	0	0
T110	0	6	0	0
T111	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	558239529	3751	0	0
TransStop_A	558239529	1898	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239529	3751	0	0
T1	260339	34	0	0
T2	342999	126	0	0
T3	0	84	0	0
T4	161364	0	0	0
T15	2329	0	0	0
T16	4797	0	0	0
T17	31711	0	0	0
T18	11179	1	0	0
T19	10801	2	0	0
T20	107032	10	0	0
T21	40983	9	0	0
T27	0	1	0	0
T28	0	13	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239529	1898	0	0
T1	260339	15	0	0
T2	342999	66	0	0
T3	0	47	0	0
T4	161364	0	0	0
T15	2329	0	0	0
T16	4797	0	0	0
T17	31711	0	0	0
T18	11179	0	0	0
T19	10801	0	0	0
T20	107032	9	0	0
T21	40983	7	0	0
T27	0	1	0	0
T28	0	8	0	0
T109	0	3	0	0
T110	0	1	0	0
T111	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	558239529	3726	0	0
TransStop_A	558239529	1884	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239529	3726	0	0
T1	260339	33	0	0
T2	342999	126	0	0
T3	0	96	0	0
T4	161364	0	0	0
T15	2329	0	0	0
T16	4797	0	0	0
T17	31711	0	0	0
T18	11179	3	0	0
T19	10801	2	0	0
T20	107032	7	0	0
T21	40983	5	0	0
T27	0	1	0	0
T28	0	13	0	0
T110	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239529	1884	0	0
T1	260339	17	0	0
T2	342999	59	0	0
T3	0	50	0	0
T4	161364	0	0	0
T15	2329	0	0	0
T16	4797	0	0	0
T17	31711	0	0	0
T18	11179	1	0	0
T19	10801	0	0	0
T20	107032	6	0	0
T21	40983	3	0	0
T27	0	1	0	0
T28	0	7	0	0
T109	0	7	0	0
T110	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	558239529	3657	0	0
TransStop_A	558239529	1839	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239529	3657	0	0
T1	260339	37	0	0
T2	342999	126	0	0
T3	0	68	0	0
T4	161364	0	0	0
T15	2329	0	0	0
T16	4797	0	0	0
T17	31711	0	0	0
T18	11179	2	0	0
T19	10801	2	0	0
T20	107032	7	0	0
T21	40983	9	0	0
T27	0	1	0	0
T28	0	12	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239529	1839	0	0
T1	260339	19	0	0
T2	342999	62	0	0
T3	0	33	0	0
T4	161364	0	0	0
T15	2329	0	0	0
T16	4797	0	0	0
T17	31711	0	0	0
T18	11179	1	0	0
T19	10801	0	0	0
T20	107032	6	0	0
T21	40983	4	0	0
T27	0	1	0	0
T28	0	6	0	0
T109	0	6	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	558239529	3692	0	0
TransStop_A	558239529	1913	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239529	3692	0	0
T1	260339	37	0	0
T2	342999	122	0	0
T3	0	78	0	0
T4	161364	0	0	0
T15	2329	0	0	0
T16	4797	0	0	0
T17	31711	0	0	0
T18	11179	1	0	0
T19	10801	2	0	0
T20	107032	10	0	0
T21	40983	10	0	0
T27	0	1	0	0
T28	0	13	0	0
T110	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239529	1913	0	0
T1	260339	18	0	0
T2	342999	63	0	0
T3	0	43	0	0
T4	161364	0	0	0
T15	2329	0	0	0
T16	4797	0	0	0
T17	31711	0	0	0
T18	11179	0	0	0
T19	10801	0	0	0
T20	107032	6	0	0
T21	40983	7	0	0
T27	0	1	0	0
T28	0	6	0	0
T109	0	5	0	0
T110	0	2	0	0
T111	0	1	0	0