Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	161935498	23665895	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161935498	23665895	0	58
T1	128449	37878	0	0
T2	240645	36662	0	0
T3	0	60980	0	0
T4	37114	883	0	1
T8	0	3870	0	0
T9	0	13023	0	1
T10	0	13288	0	1
T11	0	36714	0	1
T12	0	106480	0	0
T13	0	0	0	1
T14	0	0	0	1
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0
T26	0	718	0	1
T32	0	0	0	1
T49	0	0	0	1
T112	0	0	0	1