Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	162851139	5225693	0	0
clk_enables_rd_A	162851139	53528	0	0
clk_hints_rd_A	162851139	47428	0	0
extclk_ctrl_rd_A	162851139	59989	0	0
extclk_ctrl_regwen_rd_A	162851139	45758	0	0
jitter_enable_rd_A	162851139	67204	0	0
jitter_regwen_rd_A	162851139	50570	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162851139	5225693	0	0
T1	128449	36105	0	0
T2	240645	113791	0	0
T3	0	67878	0	0
T4	37114	0	0	0
T12	0	79137	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0
T31	0	48478	0	0
T62	0	104539	0	0
T63	0	86898	0	0
T64	0	125757	0	0
T65	0	119033	0	0
T66	0	85432	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162851139	53528	0	0
T1	128449	1371	0	0
T2	240645	0	0	0
T4	37114	0	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0
T31	0	1992	0	0
T63	0	3387	0	0
T65	0	2449	0	0
T111	0	5	0	0
T129	0	596	0	0
T130	0	1	0	0
T131	0	2781	0	0
T132	0	6	0	0
T133	0	5076	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162851139	47428	0	0
T1	128449	1195	0	0
T2	240645	0	0	0
T4	37114	0	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0
T31	0	1730	0	0
T63	0	3169	0	0
T65	0	2077	0	0
T111	0	4	0	0
T129	0	520	0	0
T130	0	3	0	0
T131	0	2356	0	0
T132	0	13	0	0
T133	0	4063	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162851139	59989	0	0
T1	128449	1363	0	0
T2	240645	0	0	0
T4	37114	0	0	0
T13	0	91	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0
T31	0	2312	0	0
T76	0	57	0	0
T94	0	11	0	0
T95	0	2	0	0
T134	0	22	0	0
T135	0	62	0	0
T136	0	67	0	0
T137	0	16	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162851139	45758	0	0
T1	128449	1077	0	0
T2	240645	0	0	0
T4	37114	0	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0
T31	0	1762	0	0
T45	0	37	0	0
T63	0	2871	0	0
T65	0	2170	0	0
T94	0	7	0	0
T95	0	1	0	0
T129	0	483	0	0
T138	0	6	0	0
T139	0	21	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162851139	67204	0	0
T1	128449	2132	0	0
T2	240645	0	0	0
T4	37114	0	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0
T31	0	2816	0	0
T63	0	4420	0	0
T65	0	3530	0	0
T111	0	122	0	0
T129	0	589	0	0
T130	0	86	0	0
T131	0	2828	0	0
T132	0	218	0	0
T133	0	5890	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162851139	50570	0	0
T1	128449	1223	0	0
T2	240645	0	0	0
T4	37114	0	0	0
T15	2328	0	0	0
T16	671	0	0	0
T17	1585	0	0	0
T18	2682	0	0	0
T19	10368	0	0	0
T20	103823	0	0	0
T21	2048	0	0	0
T31	0	1972	0	0
T35	0	6241	0	0
T63	0	3162	0	0
T65	0	2493	0	0
T129	0	602	0	0
T131	0	2968	0	0
T133	0	4826	0	0
T140	0	1697	0	0
T141	0	2311	0	0