Unified Coverage Report :: Module :: prim_clock_meas

Module : prim_clock_meas

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_meas.u_meas	93.33	100.00	100.00		100.00	100.00	66.67
tb.dut.u_io_div2_meas.u_meas	93.33	100.00	100.00		100.00	100.00	66.67
tb.dut.u_io_div4_meas.u_meas	93.33	100.00	100.00		100.00	100.00	66.67
tb.dut.u_main_meas.u_meas	93.33	100.00	100.00		100.00	100.00	66.67
tb.dut.u_usb_meas.u_meas	93.33	100.00	100.00		100.00	100.00	66.67

---

Module Instance : tb.dut.u_io_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		100.00	100.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	100.00	100.00				100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	87.50	100.00	100.00			100.00	50.00
u_ref_meas_en_sync	100.00	100.00				100.00
u_sync_ref	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		100.00	100.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div2_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	100.00	100.00				100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	87.50	100.00	100.00			100.00	50.00
u_ref_meas_en_sync	100.00	100.00				100.00
u_sync_ref	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		100.00	100.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div4_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	100.00	100.00				100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	87.50	100.00	100.00			100.00	50.00
u_ref_meas_en_sync	100.00	100.00				100.00
u_sync_ref	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_main_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		100.00	100.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_main_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	100.00	100.00				100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	87.50	100.00	100.00			100.00	50.00
u_ref_meas_en_sync	100.00	100.00				100.00
u_sync_ref	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_usb_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		100.00	100.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_usb_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	100.00	100.00				100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	87.50	100.00	100.00			100.00	50.00
u_ref_meas_en_sync	100.00	100.00				100.00
u_sync_ref	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_clock_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
89	1	1
91	1	1
100	1	1
101	1	1
103	1	1
106	1	1
107	1	1
			MISSING_ELSE
112	1	1
113	1	1
			MISSING_ELSE
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
			MISSING_ELSE
163	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1

---

Cond Coverage for Module : prim_clock_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T4,T2

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T4,T2,T3

---

FSM Coverage for Module : prim_clock_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T5,T6,T7
StDisabling	120	Covered	T1,T4,T2
StEnable	113	Covered	T1,T4,T2
StEnabling	107	Covered	T1,T4,T2

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T4,T2
StDisabling->StDisable	126	Covered	T1,T4,T2
StEnable->StDisabling	120	Covered	T1,T4,T2
StEnabling->StEnable	113	Covered	T1,T4,T2

---

Branch Coverage for Module : prim_clock_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T4,T2
StDisable	0	-	-	-	Covered	T1,T4,T2
StEnabling	-	1	-	-	Covered	T1,T4,T2
StEnabling	-	0	-	-	Covered	T1,T4,T2
StEnable	-	-	1	-	Covered	T1,T4,T2
StEnable	-	-	0	-	Covered	T1,T4,T2
StDisabling	-	-	-	1	Covered	T1,T4,T2
StDisabling	-	-	-	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T5,T6,T7
0	1	-	-	-	Covered	T1,T4,T2
0	0	1	-	-	Covered	T1,T4,T2
0	0	0	1	-	Covered	T1,T4,T2
0	0	0	0	1	Covered	T1,T4,T2
0	0	0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_clock_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	1744712792	0	0	0
RefCntVal_A	4025	4025	0	0
gen_timeout_assert.ClkRatios_A	4025	4025	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1744712792	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4025	4025	0	0
T1	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T7	5	5	0	0
T15	5	5	0	0
T16	5	5	0	0
T22	5	5	0	0
T23	5	5	0	0
T24	5	5	0	0
T25	5	5	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4025	4025	0	0
T1	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T7	5	5	0	0
T15	5	5	0	0
T16	5	5	0	0
T22	5	5	0	0
T23	5	5	0	0
T24	5	5	0	0
T25	5	5	0	0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
89	1	1
91	1	1
100	1	1
101	1	1
103	1	1
106	1	1
107	1	1
			MISSING_ELSE
112	1	1
113	1	1
			MISSING_ELSE
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
			MISSING_ELSE
163	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T4,T2

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T3,T26

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T2,T3,T26
1	0	Covered	T1,T2,T3

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T4,T2,T3

---

FSM Coverage for Instance : tb.dut.u_io_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T5,T6,T7
StDisabling	120	Covered	T1,T4,T2
StEnable	113	Covered	T1,T4,T2
StEnabling	107	Covered	T1,T4,T2

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T4,T2
StDisabling->StDisable	126	Covered	T1,T4,T2
StEnable->StDisabling	120	Covered	T1,T4,T2
StEnabling->StEnable	113	Covered	T1,T4,T2

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T4,T2
StDisable	0	-	-	-	Covered	T1,T4,T2
StEnabling	-	1	-	-	Covered	T1,T4,T2
StEnabling	-	0	-	-	Covered	T1,T4,T2
StEnable	-	-	1	-	Covered	T1,T4,T2
StEnable	-	-	0	-	Covered	T1,T4,T2
StDisabling	-	-	-	1	Covered	T1,T4,T2
StDisabling	-	-	-	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T5,T6,T7
0	1	-	-	-	Covered	T1,T4,T2
0	0	1	-	-	Covered	T1,T4,T2
0	0	0	1	-	Covered	T2,T3,T26
0	0	0	0	1	Covered	T1,T4,T2
0	0	0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	524926692	0	0	0
RefCntVal_A	805	805	0	0
gen_timeout_assert.ClkRatios_A	805	805	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524926692	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
89	1	1
91	1	1
100	1	1
101	1	1
103	1	1
106	1	1
107	1	1
			MISSING_ELSE
112	1	1
113	1	1
			MISSING_ELSE
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
			MISSING_ELSE
163	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T4,T2

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T4,T2,T3

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T3
1	0	Covered	T1,T4,T2

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T3,T12

---

FSM Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T5,T6,T7
StDisabling	120	Covered	T1,T4,T2
StEnable	113	Covered	T1,T4,T2
StEnabling	107	Covered	T1,T4,T2

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T4,T2
StDisabling->StDisable	126	Covered	T1,T4,T2
StEnable->StDisabling	120	Covered	T1,T4,T2
StEnabling->StEnable	113	Covered	T1,T4,T2

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T4,T2
StDisable	0	-	-	-	Covered	T1,T4,T2
StEnabling	-	1	-	-	Covered	T1,T4,T2
StEnabling	-	0	-	-	Covered	T1,T4,T2
StEnable	-	-	1	-	Covered	T1,T4,T2
StEnable	-	-	0	-	Covered	T1,T4,T2
StDisabling	-	-	-	1	Covered	T1,T4,T2
StDisabling	-	-	-	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T5,T6,T7
0	1	-	-	-	Covered	T1,T4,T2
0	0	1	-	-	Covered	T1,T4,T2
0	0	0	1	-	Covered	T4,T2,T3
0	0	0	0	1	Covered	T1,T4,T2
0	0	0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	262463522	0	0	0
RefCntVal_A	805	805	0	0
gen_timeout_assert.ClkRatios_A	805	805	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463522	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
89	1	1
91	1	1
100	1	1
101	1	1
103	1	1
106	1	1
107	1	1
			MISSING_ELSE
112	1	1
113	1	1
			MISSING_ELSE
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
			MISSING_ELSE
163	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T4,T2

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T31,T32

---

FSM Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T5,T6,T7
StDisabling	120	Covered	T1,T4,T2
StEnable	113	Covered	T1,T4,T2
StEnabling	107	Covered	T1,T4,T2

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T4,T2
StDisabling->StDisable	126	Covered	T1,T4,T2
StEnable->StDisabling	120	Covered	T1,T4,T2
StEnabling->StEnable	113	Covered	T1,T4,T2

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T4,T2
StDisable	0	-	-	-	Covered	T1,T4,T2
StEnabling	-	1	-	-	Covered	T1,T4,T2
StEnabling	-	0	-	-	Covered	T1,T4,T2
StEnable	-	-	1	-	Covered	T1,T4,T2
StEnable	-	-	0	-	Covered	T1,T4,T2
StDisabling	-	-	-	1	Covered	T1,T4,T2
StDisabling	-	-	-	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T5,T6,T7
0	1	-	-	-	Covered	T1,T4,T2
0	0	1	-	-	Covered	T1,T4,T2
0	0	0	1	-	Covered	T1,T4,T2
0	0	0	0	1	Covered	T1,T4,T2
0	0	0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	131231101	0	0	0
RefCntVal_A	805	805	0	0
gen_timeout_assert.ClkRatios_A	805	805	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231101	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
89	1	1
91	1	1
100	1	1
101	1	1
103	1	1
106	1	1
107	1	1
			MISSING_ELSE
112	1	1
113	1	1
			MISSING_ELSE
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
			MISSING_ELSE
163	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T4,T2

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T12,T13

---

FSM Coverage for Instance : tb.dut.u_main_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T5,T6,T7
StDisabling	120	Covered	T1,T4,T2
StEnable	113	Covered	T1,T4,T2
StEnabling	107	Covered	T1,T4,T2

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T4,T2
StDisabling->StDisable	126	Covered	T1,T4,T2
StEnable->StDisabling	120	Covered	T1,T4,T2
StEnabling->StEnable	113	Covered	T1,T4,T2

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T4,T2
StDisable	0	-	-	-	Covered	T1,T4,T2
StEnabling	-	1	-	-	Covered	T1,T4,T2
StEnabling	-	0	-	-	Covered	T1,T4,T2
StEnable	-	-	1	-	Covered	T1,T4,T2
StEnable	-	-	0	-	Covered	T1,T4,T2
StDisabling	-	-	-	1	Covered	T1,T4,T2
StDisabling	-	-	-	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T5,T6,T7
0	1	-	-	-	Covered	T1,T4,T2
0	0	1	-	-	Covered	T1,T4,T2
0	0	0	1	-	Covered	T1,T4,T2
0	0	0	0	1	Covered	T1,T4,T2
0	0	0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	558239095	0	0	0
RefCntVal_A	805	805	0	0
gen_timeout_assert.ClkRatios_A	805	805	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
89	1	1
91	1	1
100	1	1
101	1	1
103	1	1
106	1	1
107	1	1
			MISSING_ELSE
112	1	1
113	1	1
			MISSING_ELSE
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
			MISSING_ELSE
163	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T4,T2

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T4,T2,T3

---

FSM Coverage for Instance : tb.dut.u_usb_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T5,T6,T7
StDisabling	120	Covered	T1,T4,T2
StEnable	113	Covered	T1,T4,T2
StEnabling	107	Covered	T1,T4,T2

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T4,T2
StDisabling->StDisable	126	Covered	T1,T4,T2
StEnable->StDisabling	120	Covered	T1,T4,T2
StEnabling->StEnable	113	Covered	T1,T4,T2

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T4,T2
StDisable	0	-	-	-	Covered	T1,T4,T2
StEnabling	-	1	-	-	Covered	T1,T4,T2
StEnabling	-	0	-	-	Covered	T1,T4,T2
StEnable	-	-	1	-	Covered	T1,T4,T2
StEnable	-	-	0	-	Covered	T1,T4,T2
StDisabling	-	-	-	1	Covered	T1,T4,T2
StDisabling	-	-	-	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T5,T6,T7
0	1	-	-	-	Covered	T1,T4,T2
0	0	1	-	-	Covered	T1,T4,T2
0	0	0	1	-	Covered	T1,T4,T2
0	0	0	0	1	Covered	T1,T4,T2
0	0	0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	267852382	0	0	0
RefCntVal_A	805	805	0	0
gen_timeout_assert.ClkRatios_A	805	805	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267852382	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0