Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T24
1	1	Covered	T5,T6,T23

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	524927125	4567	0	0
g_div2.Div2Whole_A	524927125	5477	0	0
g_div4.Div4Stepped_A	262463944	4459	0	0
g_div4.Div4Whole_A	262463944	5119	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524927125	4567	0	0
T1	235518	17	0	0
T2	0	108	0	0
T5	4978	4	0	0
T6	4756	7	0	0
T7	3331	0	0	0
T15	2235	8	0	0
T16	4604	0	0	0
T17	0	15	0	0
T19	0	25	0	0
T22	2680	0	0	0
T23	1534	4	0	0
T24	3073	3	0	0
T25	8535	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524927125	5477	0	0
T1	235518	17	0	0
T2	0	110	0	0
T5	4978	4	0	0
T6	4756	10	0	0
T7	3331	0	0	0
T15	2235	10	0	0
T16	4604	0	0	0
T17	0	15	0	0
T19	0	38	0	0
T22	2680	0	0	0
T23	1534	5	0	0
T24	3073	4	0	0
T25	8535	4	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463944	4459	0	0
T1	117618	17	0	0
T2	0	108	0	0
T5	2591	4	0	0
T6	2560	7	0	0
T7	1633	0	0	0
T15	1189	6	0	0
T16	2256	0	0	0
T17	0	15	0	0
T19	0	22	0	0
T22	1301	0	0	0
T23	833	4	0	0
T24	1571	3	0	0
T25	4504	4	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463944	5119	0	0
T1	117618	17	0	0
T2	0	110	0	0
T5	2591	4	0	0
T6	2560	10	0	0
T7	1633	0	0	0
T15	1189	7	0	0
T16	2256	0	0	0
T17	0	15	0	0
T19	0	27	0	0
T22	1301	0	0	0
T23	833	4	0	0
T24	1571	4	0	0
T25	4504	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T24
1	1	Covered	T5,T6,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	524927125	4567	0	0
g_div2.Div2Whole_A	524927125	5477	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524927125	4567	0	0
T1	235518	17	0	0
T2	0	108	0	0
T5	4978	4	0	0
T6	4756	7	0	0
T7	3331	0	0	0
T15	2235	8	0	0
T16	4604	0	0	0
T17	0	15	0	0
T19	0	25	0	0
T22	2680	0	0	0
T23	1534	4	0	0
T24	3073	3	0	0
T25	8535	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524927125	5477	0	0
T1	235518	17	0	0
T2	0	110	0	0
T5	4978	4	0	0
T6	4756	10	0	0
T7	3331	0	0	0
T15	2235	10	0	0
T16	4604	0	0	0
T17	0	15	0	0
T19	0	38	0	0
T22	2680	0	0	0
T23	1534	5	0	0
T24	3073	4	0	0
T25	8535	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T24
1	1	Covered	T5,T6,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	262463944	4459	0	0
g_div4.Div4Whole_A	262463944	5119	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463944	4459	0	0
T1	117618	17	0	0
T2	0	108	0	0
T5	2591	4	0	0
T6	2560	7	0	0
T7	1633	0	0	0
T15	1189	6	0	0
T16	2256	0	0	0
T17	0	15	0	0
T19	0	22	0	0
T22	1301	0	0	0
T23	833	4	0	0
T24	1571	3	0	0
T25	4504	4	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463944	5119	0	0
T1	117618	17	0	0
T2	0	110	0	0
T5	2591	4	0	0
T6	2560	10	0	0
T7	1633	0	0	0
T15	1189	7	0	0
T16	2256	0	0	0
T17	0	15	0	0
T19	0	27	0	0
T22	1301	0	0	0
T23	833	4	0	0
T24	1571	4	0	0
T25	4504	3	0	0