Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47475	0	0
CgEnOn_A	2147483647	38542	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47475	0	0
T1	1201566	166	0	0
T5	8862	3	0	0
T6	8594	3	0	0
T7	5779	15	0	0
T9	147309	0	0	0
T10	173051	0	0	0
T12	0	5	0	0
T15	6345	3	0	0
T16	12784	7	0	0
T17	31710	0	0	0
T18	0	1	0	0
T22	4630	3	0	0
T23	2781	3	0	0
T24	5428	3	0	0
T25	15288	3	0	0
T37	3983	10	0	0
T38	0	15	0	0
T39	0	5	0	0
T64	0	5	0	0
T135	17706	0	0	0
T142	0	10	0	0
T143	0	15	0	0
T144	0	10	0	0
T145	0	15	0	0
T146	0	15	0	0
T149	7014	0	0	0
T150	6845	0	0	0
T151	94773	0	0	0
T152	3439	0	0	0
T153	2810	0	0	0
T154	23486	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38542	0	0
T1	1201566	77	0	0
T2	0	218	0	0
T3	0	121	0	0
T7	5779	8	0	0
T9	147309	0	0	0
T10	173051	0	0	0
T12	0	4	0	0
T15	6345	0	0	0
T16	12784	3	0	0
T17	88777	0	0	0
T18	29818	14	0	0
T19	10801	9	0	0
T20	0	42	0	0
T22	4630	0	0	0
T23	2781	0	0	0
T24	5428	0	0	0
T25	15288	0	0	0
T27	0	59	0	0
T28	0	56	0	0
T37	3983	10	0	0
T38	0	15	0	0
T39	0	5	0	0
T64	0	4	0	0
T135	17706	0	0	0
T142	0	10	0	0
T143	0	15	0	0
T144	0	10	0	0
T145	0	15	0	0
T146	0	15	0	0
T147	0	5	0	0
T149	7014	0	0	0
T150	6845	0	0	0
T151	94773	0	0	0
T152	3439	0	0	0
T153	2810	0	0	0
T154	23486	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	262463522	154	0	0
CgEnOn_A	262463522	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463522	154	0	0
T9	32705	0	0	0
T10	38444	0	0	0
T12	0	1	0	0
T37	867	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T64	0	1	0	0
T135	4022	0	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	3	0	0
T149	1532	0	0	0
T150	1501	0	0	0
T151	21046	0	0	0
T152	740	0	0	0
T153	610	0	0	0
T154	5195	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463522	154	0	0
T9	32705	0	0	0
T10	38444	0	0	0
T12	0	1	0	0
T37	867	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T64	0	1	0	0
T135	4022	0	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	3	0	0
T149	1532	0	0	0
T150	1501	0	0	0
T151	21046	0	0	0
T152	740	0	0	0
T153	610	0	0	0
T154	5195	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	131231101	154	0	0
CgEnOn_A	131231101	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231101	154	0	0
T9	16353	0	0	0
T10	19222	0	0	0
T12	0	1	0	0
T37	434	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T64	0	1	0	0
T135	2011	0	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	3	0	0
T149	766	0	0	0
T150	750	0	0	0
T151	10523	0	0	0
T152	369	0	0	0
T153	305	0	0	0
T154	2598	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231101	154	0	0
T9	16353	0	0	0
T10	19222	0	0	0
T12	0	1	0	0
T37	434	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T64	0	1	0	0
T135	2011	0	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	3	0	0
T149	766	0	0	0
T150	750	0	0	0
T151	10523	0	0	0
T152	369	0	0	0
T153	305	0	0	0
T154	2598	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524926692	154	0	0
CgEnOn_A	524926692	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524926692	154	0	0
T9	65545	0	0	0
T10	76941	0	0	0
T12	0	1	0	0
T37	1814	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T64	0	1	0	0
T135	7651	0	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	3	0	0
T149	3184	0	0	0
T150	3094	0	0	0
T151	42158	0	0	0
T152	1592	0	0	0
T153	1285	0	0	0
T154	10497	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524926692	141	0	0
T9	65545	0	0	0
T10	76941	0	0	0
T37	1814	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T135	7651	0	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	3	0	0
T147	0	5	0	0
T148	0	4	0	0
T149	3184	0	0	0
T150	3094	0	0	0
T151	42158	0	0	0
T152	1592	0	0	0
T153	1285	0	0	0
T154	10497	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558239095	139	0	0
CgEnOn_A	558239095	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	139	0	0
T9	68279	0	0	0
T10	80148	0	0	0
T37	1790	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T135	7970	0	0	0
T142	0	2	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T149	3317	0	0	0
T150	3223	0	0	0
T151	43916	0	0	0
T152	1658	0	0	0
T153	1338	0	0	0
T154	10934	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	139	0	0
T9	68279	0	0	0
T10	80148	0	0	0
T37	1790	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T135	7970	0	0	0
T142	0	2	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T149	3317	0	0	0
T150	3223	0	0	0
T151	43916	0	0	0
T152	1658	0	0	0
T153	1338	0	0	0
T154	10934	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	131231101	154	0	0
CgEnOn_A	131231101	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231101	154	0	0
T9	16353	0	0	0
T10	19222	0	0	0
T12	0	1	0	0
T37	434	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T64	0	1	0	0
T135	2011	0	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	3	0	0
T149	766	0	0	0
T150	750	0	0	0
T151	10523	0	0	0
T152	369	0	0	0
T153	305	0	0	0
T154	2598	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231101	154	0	0
T9	16353	0	0	0
T10	19222	0	0	0
T12	0	1	0	0
T37	434	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T64	0	1	0	0
T135	2011	0	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	3	0	0
T149	766	0	0	0
T150	750	0	0	0
T151	10523	0	0	0
T152	369	0	0	0
T153	305	0	0	0
T154	2598	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558239095	139	0	0
CgEnOn_A	558239095	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	139	0	0
T9	68279	0	0	0
T10	80148	0	0	0
T37	1790	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T135	7970	0	0	0
T142	0	2	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T149	3317	0	0	0
T150	3223	0	0	0
T151	43916	0	0	0
T152	1658	0	0	0
T153	1338	0	0	0
T154	10934	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	139	0	0
T9	68279	0	0	0
T10	80148	0	0	0
T37	1790	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T135	7970	0	0	0
T142	0	2	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T149	3317	0	0	0
T150	3223	0	0	0
T151	43916	0	0	0
T152	1658	0	0	0
T153	1338	0	0	0
T154	10934	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	131231101	154	0	0
CgEnOn_A	131231101	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231101	154	0	0
T9	16353	0	0	0
T10	19222	0	0	0
T12	0	1	0	0
T37	434	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T64	0	1	0	0
T135	2011	0	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	3	0	0
T149	766	0	0	0
T150	750	0	0	0
T151	10523	0	0	0
T152	369	0	0	0
T153	305	0	0	0
T154	2598	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231101	154	0	0
T9	16353	0	0	0
T10	19222	0	0	0
T12	0	1	0	0
T37	434	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T64	0	1	0	0
T135	2011	0	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	3	0	0
T149	766	0	0	0
T150	750	0	0	0
T151	10523	0	0	0
T152	369	0	0	0
T153	305	0	0	0
T154	2598	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	262463522	7744	0	0
CgEnOn_A	262463522	5521	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463522	7744	0	0
T1	117618	44	0	0
T5	2590	1	0	0
T6	2560	1	0	0
T7	1632	5	0	0
T15	1189	1	0	0
T16	2256	3	0	0
T22	1300	1	0	0
T23	832	1	0	0
T24	1571	1	0	0
T25	4503	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463522	5521	0	0
T1	117618	38	0	0
T2	0	109	0	0
T3	0	61	0	0
T7	1632	4	0	0
T15	1189	0	0	0
T16	2256	2	0	0
T17	17752	0	0	0
T18	5272	7	0	0
T19	0	5	0	0
T20	0	20	0	0
T22	1300	0	0	0
T23	832	0	0	0
T24	1571	0	0	0
T25	4503	0	0	0
T27	0	29	0	0
T28	0	28	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	131231101	7722	0	0
CgEnOn_A	131231101	5499	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231101	7722	0	0
T1	588091	45	0	0
T5	1294	1	0	0
T6	1278	1	0	0
T7	816	5	0	0
T15	593	1	0	0
T16	1128	2	0	0
T22	650	1	0	0
T23	416	1	0	0
T24	784	1	0	0
T25	2251	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231101	5499	0	0
T1	588091	39	0	0
T2	0	109	0	0
T3	0	60	0	0
T7	816	4	0	0
T15	593	0	0	0
T16	1128	1	0	0
T17	8874	0	0	0
T18	2636	7	0	0
T19	0	4	0	0
T20	0	22	0	0
T22	650	0	0	0
T23	416	0	0	0
T24	784	0	0	0
T25	2251	0	0	0
T27	0	30	0	0
T28	0	28	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524926692	7789	0	0
CgEnOn_A	524926692	5553	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524926692	7789	0	0
T1	235518	43	0	0
T5	4978	1	0	0
T6	4756	1	0	0
T7	3331	5	0	0
T15	2235	1	0	0
T16	4604	2	0	0
T22	2680	1	0	0
T23	1533	1	0	0
T24	3073	1	0	0
T25	8534	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524926692	5553	0	0
T1	235518	37	0	0
T2	0	111	0	0
T3	0	64	0	0
T7	3331	4	0	0
T15	2235	0	0	0
T16	4604	1	0	0
T17	30441	0	0	0
T18	10731	8	0	0
T19	0	4	0	0
T20	0	20	0	0
T22	2680	0	0	0
T23	1533	0	0	0
T24	3073	0	0	0
T25	8534	0	0	0
T27	0	29	0	0
T28	0	27	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	267852382	7790	0	0
CgEnOn_A	267852382	5552	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267852382	7790	0	0
T1	123237	41	0	0
T5	2489	1	0	0
T6	2378	1	0	0
T7	1665	5	0	0
T15	1117	1	0	0
T16	2302	2	0	0
T22	1339	1	0	0
T23	767	1	0	0
T24	1536	1	0	0
T25	4267	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267852382	5552	0	0
T1	123237	35	0	0
T2	0	103	0	0
T3	0	58	0	0
T7	1665	4	0	0
T15	1117	0	0	0
T16	2302	1	0	0
T17	15221	0	0	0
T18	5365	7	0	0
T19	0	4	0	0
T20	0	23	0	0
T22	1339	0	0	0
T23	767	0	0	0
T24	1536	0	0	0
T25	4267	0	0	0
T27	0	27	0	0
T28	0	27	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T1,T18,T19
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558239095	3890	0	0
CgEnOn_A	558239095	3890	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	3890	0	0
T1	260339	34	0	0
T2	342999	126	0	0
T3	0	84	0	0
T4	161363	0	0	0
T15	2328	0	0	0
T16	4796	0	0	0
T17	31710	0	0	0
T18	11179	1	0	0
T19	10801	2	0	0
T20	107031	10	0	0
T21	40983	9	0	0
T27	0	1	0	0
T28	0	13	0	0
T110	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	3890	0	0
T1	260339	34	0	0
T2	342999	126	0	0
T3	0	84	0	0
T4	161363	0	0	0
T15	2328	0	0	0
T16	4796	0	0	0
T17	31710	0	0	0
T18	11179	1	0	0
T19	10801	2	0	0
T20	107031	10	0	0
T21	40983	9	0	0
T27	0	1	0	0
T28	0	13	0	0
T110	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T1,T18,T19
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558239095	3865	0	0
CgEnOn_A	558239095	3865	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	3865	0	0
T1	260339	33	0	0
T2	342999	126	0	0
T3	0	96	0	0
T4	161363	0	0	0
T15	2328	0	0	0
T16	4796	0	0	0
T17	31710	0	0	0
T18	11179	3	0	0
T19	10801	2	0	0
T20	107031	7	0	0
T21	40983	5	0	0
T27	0	1	0	0
T28	0	13	0	0
T110	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	3865	0	0
T1	260339	33	0	0
T2	342999	126	0	0
T3	0	96	0	0
T4	161363	0	0	0
T15	2328	0	0	0
T16	4796	0	0	0
T17	31710	0	0	0
T18	11179	3	0	0
T19	10801	2	0	0
T20	107031	7	0	0
T21	40983	5	0	0
T27	0	1	0	0
T28	0	13	0	0
T110	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T1,T18,T19
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558239095	3796	0	0
CgEnOn_A	558239095	3796	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	3796	0	0
T1	260339	37	0	0
T2	342999	126	0	0
T3	0	68	0	0
T4	161363	0	0	0
T15	2328	0	0	0
T16	4796	0	0	0
T17	31710	0	0	0
T18	11179	2	0	0
T19	10801	2	0	0
T20	107031	7	0	0
T21	40983	9	0	0
T27	0	1	0	0
T28	0	12	0	0
T110	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	3796	0	0
T1	260339	37	0	0
T2	342999	126	0	0
T3	0	68	0	0
T4	161363	0	0	0
T15	2328	0	0	0
T16	4796	0	0	0
T17	31710	0	0	0
T18	11179	2	0	0
T19	10801	2	0	0
T20	107031	7	0	0
T21	40983	9	0	0
T27	0	1	0	0
T28	0	12	0	0
T110	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T1,T18,T19
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558239095	3831	0	0
CgEnOn_A	558239095	3831	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	3831	0	0
T1	260339	37	0	0
T2	342999	122	0	0
T3	0	78	0	0
T4	161363	0	0	0
T15	2328	0	0	0
T16	4796	0	0	0
T17	31710	0	0	0
T18	11179	1	0	0
T19	10801	2	0	0
T20	107031	10	0	0
T21	40983	10	0	0
T27	0	1	0	0
T28	0	13	0	0
T110	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558239095	3831	0	0
T1	260339	37	0	0
T2	342999	122	0	0
T3	0	78	0	0
T4	161363	0	0	0
T15	2328	0	0	0
T16	4796	0	0	0
T17	31710	0	0	0
T18	11179	1	0	0
T19	10801	2	0	0
T20	107031	10	0	0
T21	40983	10	0	0
T27	0	1	0	0
T28	0	13	0	0
T110	0	2	0	0