Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T16
0	1	Covered	T7,T1,T16
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T16
1	0	Covered	T37,T38,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1186475360	14198	0	0
GateOpen_A	1186475360	14198	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1186475360	14198	0	0
T1	1064464	91	0	0
T2	0	292	0	0
T3	0	175	0	0
T7	7447	13	0	0
T15	5135	0	0	0
T16	10290	5	0	0
T17	72288	0	0	0
T18	24007	12	0	0
T19	0	4	0	0
T20	0	42	0	0
T22	5972	0	0	0
T23	3550	0	0	0
T24	6966	0	0	0
T25	19558	0	0	0
T27	0	77	0	0
T28	0	68	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1186475360	14198	0	0
T1	1064464	91	0	0
T2	0	292	0	0
T3	0	175	0	0
T7	7447	13	0	0
T15	5135	0	0	0
T16	10290	5	0	0
T17	72288	0	0	0
T18	24007	12	0	0
T19	0	4	0	0
T20	0	42	0	0
T22	5972	0	0	0
T23	3550	0	0	0
T24	6966	0	0	0
T25	19558	0	0	0
T27	0	77	0	0
T28	0	68	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T16
0	1	Covered	T7,T1,T16
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T16
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	131231512	3536	0	0
GateOpen_A	131231512	3536	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231512	3536	0	0
T1	588091	25	0	0
T2	0	74	0	0
T3	0	42	0	0
T7	817	3	0	0
T15	593	0	0	0
T16	1128	1	0	0
T17	8874	0	0	0
T18	2637	2	0	0
T19	0	1	0	0
T20	0	9	0	0
T22	651	0	0	0
T23	416	0	0	0
T24	785	0	0	0
T25	2252	0	0	0
T27	0	21	0	0
T28	0	17	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131231512	3536	0	0
T1	588091	25	0	0
T2	0	74	0	0
T3	0	42	0	0
T7	817	3	0	0
T15	593	0	0	0
T16	1128	1	0	0
T17	8874	0	0	0
T18	2637	2	0	0
T19	0	1	0	0
T20	0	9	0	0
T22	651	0	0	0
T23	416	0	0	0
T24	785	0	0	0
T25	2252	0	0	0
T27	0	21	0	0
T28	0	17	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T16
0	1	Covered	T7,T1,T16
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T16
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	262463944	3521	0	0
GateOpen_A	262463944	3521	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463944	3521	0	0
T1	117618	24	0	0
T2	0	72	0	0
T3	0	44	0	0
T7	1633	4	0	0
T15	1189	0	0	0
T16	2256	2	0	0
T17	17752	0	0	0
T18	5272	2	0	0
T19	0	1	0	0
T20	0	11	0	0
T22	1301	0	0	0
T23	833	0	0	0
T24	1571	0	0	0
T25	4504	0	0	0
T27	0	18	0	0
T28	0	17	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	262463944	3521	0	0
T1	117618	24	0	0
T2	0	72	0	0
T3	0	44	0	0
T7	1633	4	0	0
T15	1189	0	0	0
T16	2256	2	0	0
T17	17752	0	0	0
T18	5272	2	0	0
T19	0	1	0	0
T20	0	11	0	0
T22	1301	0	0	0
T23	833	0	0	0
T24	1571	0	0	0
T25	4504	0	0	0
T27	0	18	0	0
T28	0	17	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T16
0	1	Covered	T7,T1,T16
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T16
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	524927125	3562	0	0
GateOpen_A	524927125	3562	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524927125	3562	0	0
T1	235518	22	0	0
T2	0	76	0	0
T3	0	45	0	0
T7	3331	3	0	0
T15	2235	0	0	0
T16	4604	1	0	0
T17	30441	0	0	0
T18	10732	4	0	0
T19	0	1	0	0
T20	0	11	0	0
T22	2680	0	0	0
T23	1534	0	0	0
T24	3073	0	0	0
T25	8535	0	0	0
T27	0	20	0	0
T28	0	18	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524927125	3562	0	0
T1	235518	22	0	0
T2	0	76	0	0
T3	0	45	0	0
T7	3331	3	0	0
T15	2235	0	0	0
T16	4604	1	0	0
T17	30441	0	0	0
T18	10732	4	0	0
T19	0	1	0	0
T20	0	11	0	0
T22	2680	0	0	0
T23	1534	0	0	0
T24	3073	0	0	0
T25	8535	0	0	0
T27	0	20	0	0
T28	0	18	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T16
0	1	Covered	T7,T1,T16
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T16
1	0	Covered	T37,T38,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	267852779	3579	0	0
GateOpen_A	267852779	3579	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267852779	3579	0	0
T1	123237	20	0	0
T2	0	70	0	0
T3	0	44	0	0
T7	1666	3	0	0
T15	1118	0	0	0
T16	2302	1	0	0
T17	15221	0	0	0
T18	5366	4	0	0
T19	0	1	0	0
T20	0	11	0	0
T22	1340	0	0	0
T23	767	0	0	0
T24	1537	0	0	0
T25	4267	0	0	0
T27	0	18	0	0
T28	0	16	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267852779	3579	0	0
T1	123237	20	0	0
T2	0	70	0	0
T3	0	44	0	0
T7	1666	3	0	0
T15	1118	0	0	0
T16	2302	1	0	0
T17	15221	0	0	0
T18	5366	4	0	0
T19	0	1	0	0
T20	0	11	0	0
T22	1340	0	0	0
T23	767	0	0	0
T24	1537	0	0	0
T25	4267	0	0	0
T27	0	18	0	0
T28	0	16	0	0