Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	93.75	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

16 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack	0.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if	100.00	1	100	1	64	64

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	6	0	0.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	6	0	0.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	6	0	0.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
false	0	1	1
true	0	1	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	152	1			T1	2		T18	1		T105	1
others[1]	158	1			T5	1		T18	2		T105	1
others[2]	3639	1			T5	18		T1	15		T16	8
others[3]	283	1			T5	1		T16	1		T4	8
false	814	1			T5	2		T1	5		T16	2
true	2482	1			T5	12		T1	8		T16	5

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	110	1			T5	1		T18	2		T105	1
others[1]	107	1			T5	1		T1	1		T159	1
others[2]	3574	1			T5	18		T1	15		T16	8
others[3]	190	1			T16	1		T104	1		T105	1
false	541	1			T5	1		T1	2		T16	1
true	3006	1			T5	13		T1	12		T16	6

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	561	1			T1	18		T4	2		T19	2
others[1]	519	1			T1	11		T19	3		T20	3
others[2]	534	1			T1	15		T4	1		T19	2
others[3]	956	1			T1	21		T4	1		T19	3
false	3768	1			T1	84		T4	11		T19	13
true	906	1			T1	19		T4	1		T19	3

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	576	1			T1	15		T4	2		T19	2
others[1]	536	1			T1	14		T19	2		T20	1
others[2]	605	1			T1	15		T4	1		T19	2
others[3]	888	1			T1	19		T4	3		T19	3
false	3759	1			T1	84		T4	9		T19	13
true	880	1			T1	21		T4	1		T19	4

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	521	1			T1	20		T20	3		T23	7
others[1]	571	1			T1	15		T4	1		T19	4
others[2]	579	1			T1	15		T4	1		T19	2
others[3]	909	1			T1	24		T4	1		T19	1
false	3759	1			T1	84		T4	11		T19	13
true	905	1			T1	10		T4	2		T19	6

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	2451	1			T1	19		T17	19		T12	19
others[1]	387	1			T1	3		T17	3		T12	3
others[2]	387	1			T1	3		T17	3		T12	3
others[3]	645	1			T1	5		T17	5		T12	5
false	129	1			T1	1		T17	1		T12	1
true	129	1			T1	1		T17	1		T12	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	557	1			T1	17		T4	1		T19	1
others[1]	572	1			T1	10		T4	3		T19	2
others[2]	542	1			T1	18		T19	1		T20	2
others[3]	922	1			T1	24		T19	5		T20	3
false	3763	1			T1	84		T4	9		T19	13
true	888	1			T1	15		T4	3		T19	4

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	566	1			T1	11		T20	1		T23	4
others[1]	555	1			T1	12		T4	2		T19	6
others[2]	557	1			T1	15		T4	1		T20	2
others[3]	882	1			T1	24		T4	1		T19	6
false	3773	1			T1	84		T4	9		T19	13
true	911	1			T1	22		T4	3		T19	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	1540	1			T5	3		T1	2		T2	11
others[1]	1483	1			T5	3		T1	2		T2	13
others[2]	1329	1			T5	6		T1	6		T2	16
others[3]	2466	1			T5	10		T1	2		T2	20
false	5438	1			T5	5		T6	1		T1	14
true	3999	1			T5	9		T1	5		T2	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	1984	1			T5	2		T1	4		T2	18
others[1]	1960	1			T5	4		T1	3		T2	23
others[2]	1796	1			T5	4		T1	1		T2	14
others[3]	3236	1			T5	9		T1	2		T2	31
false	5982	1			T5	6		T6	1		T1	18
true	6541	1			T5	14		T1	9		T2	63

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	703	1			T1	1		T2	16		T17	1
others[1]	93	1			T6	1		T22	1		T109	1
others[2]	118	1			T22	1		T109	4		T160	3
others[3]	203	1			T6	1		T22	2		T109	9
false	10568	1			T5	4		T1	21		T2	141
true	11772	1			T5	5		T6	3		T1	32

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	693	1			T6	1		T1	1		T2	16
others[1]	125	1			T22	1		T109	2		T160	2
others[2]	107	1			T6	1		T109	1		T161	4
others[3]	192	1			T22	2		T109	11		T161	5
false	10537	1			T5	4		T6	1		T1	23
true	11733	1			T5	4		T6	3		T1	34

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	715	1			T1	1		T2	16		T17	1
others[1]	126	1			T109	4		T160	1		T161	3
others[2]	79	1			T109	3		T161	2		T162	3
others[3]	197	1			T6	2		T22	4		T109	9
false	10510	1			T5	5		T6	1		T1	18
true	11731	1			T5	5		T6	3		T1	29

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	714	1			T1	1		T2	16		T17	1
others[1]	110	1			T22	1		T109	4		T160	1
others[2]	104	1			T6	1		T22	1		T109	9
others[3]	189	1			T6	1		T22	3		T109	4
false	10610	1			T5	5		T6	2		T1	21
true	11777	1			T5	5		T6	3		T1	32

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	889	1			T5	1		T1	1		T2	11
others[1]	993	1			T5	3		T2	5		T16	2
others[2]	935	1			T5	5		T1	2		T2	10
others[3]	1585	1			T5	6		T1	2		T2	17
false	5035	1			T5	11		T6	1		T1	12
true	5181	1			T5	11		T1	6		T2	52