Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	592629	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3368445

1

T5

32

T6

5

T1

1056

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	976947	1			T5	30		T6	8		T1	305
values[0x0]	1371947	1			T5	15		T6	3		T1	975
values[0x1]	1612180	1			T5	20		T6	3		T1	973

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	328795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3632279

1

T5

34

T6

5

T1

1383

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15117	1			T1	6		T2	389		T4	3
valid_sources[0x01]	14949	1			T1	6		T2	409		T4	1
valid_sources[0x02]	15996	1			T1	8		T2	239		T4	1
valid_sources[0x03]	14579	1			T1	13		T2	366		T4	1
valid_sources[0x04]	15510	1			T5	1		T1	9		T2	400
valid_sources[0x05]	15400	1			T1	7		T2	457		T4	1
valid_sources[0x06]	15759	1			T1	20		T2	398		T4	2
valid_sources[0x07]	14968	1			T1	13		T2	419		T4	1
valid_sources[0x08]	16062	1			T1	5		T2	368		T4	1
valid_sources[0x09]	14276	1			T1	9		T2	440		T4	2
valid_sources[0x0a]	14819	1			T1	10		T2	490		T4	4
valid_sources[0x0b]	14909	1			T1	5		T2	363		T20	2
valid_sources[0x0c]	14699	1			T5	1		T1	7		T2	281
valid_sources[0x0d]	15427	1			T5	1		T1	7		T2	327
valid_sources[0x0e]	15351	1			T1	9		T2	429		T4	1
valid_sources[0x0f]	17227	1			T5	2		T1	12		T2	443
valid_sources[0x10]	15464	1			T1	12		T2	393		T16	1
valid_sources[0x11]	15320	1			T1	6		T2	327		T20	2
valid_sources[0x12]	15279	1			T1	8		T2	315		T23	3
valid_sources[0x13]	15594	1			T1	6		T2	392		T4	2
valid_sources[0x14]	15247	1			T1	10		T2	399		T22	1
valid_sources[0x15]	15136	1			T1	11		T2	365		T4	2
valid_sources[0x16]	15637	1			T5	1		T1	11		T2	399
valid_sources[0x17]	14504	1			T1	9		T2	222		T4	1
valid_sources[0x18]	14565	1			T5	1		T1	10		T2	315
valid_sources[0x19]	16098	1			T1	6		T2	321		T19	3
valid_sources[0x1a]	14547	1			T1	10		T2	422		T4	3
valid_sources[0x1b]	15094	1			T1	13		T2	349		T4	1
valid_sources[0x1c]	17009	1			T1	8		T2	392		T23	1
valid_sources[0x1d]	15828	1			T1	9		T2	480		T20	5
valid_sources[0x1e]	16541	1			T1	10		T2	477		T4	1
valid_sources[0x1f]	15386	1			T1	10		T2	351		T19	1
valid_sources[0x20]	15930	1			T1	6		T2	359		T20	3
valid_sources[0x21]	16362	1			T1	5		T2	332		T23	1
valid_sources[0x22]	15058	1			T1	15		T2	366		T19	10
valid_sources[0x23]	14372	1			T1	7		T2	465		T19	14
valid_sources[0x24]	14881	1			T1	8		T2	420		T4	1
valid_sources[0x25]	14966	1			T1	7		T2	494		T16	1
valid_sources[0x26]	15987	1			T1	6		T2	333		T20	1
valid_sources[0x27]	16280	1			T1	11		T2	324		T23	3
valid_sources[0x28]	15586	1			T1	9		T2	340		T4	3
valid_sources[0x29]	14299	1			T1	8		T2	395		T4	7
valid_sources[0x2a]	15178	1			T1	10		T2	470		T19	2
valid_sources[0x2b]	15711	1			T1	5		T2	381		T4	3
valid_sources[0x2c]	16305	1			T6	3		T1	7		T2	386
valid_sources[0x2d]	14933	1			T1	10		T2	341		T4	3
valid_sources[0x2e]	15858	1			T1	7		T2	336		T4	2
valid_sources[0x2f]	16597	1			T1	11		T2	392		T4	1
valid_sources[0x30]	14860	1			T1	9		T2	340		T16	1
valid_sources[0x31]	15124	1			T1	13		T2	278		T4	2
valid_sources[0x32]	15510	1			T5	2		T1	8		T2	348
valid_sources[0x33]	14848	1			T1	10		T2	311		T20	2
valid_sources[0x34]	15496	1			T5	2		T1	17		T2	420
valid_sources[0x35]	15335	1			T5	1		T1	4		T2	260
valid_sources[0x36]	16596	1			T5	1		T1	5		T2	409
valid_sources[0x37]	14723	1			T1	14		T2	427		T4	1
valid_sources[0x38]	15441	1			T1	8		T2	297		T20	3
valid_sources[0x39]	14442	1			T1	7		T2	397		T4	2
valid_sources[0x3a]	16140	1			T1	13		T2	437		T23	3
valid_sources[0x3b]	16438	1			T1	12		T2	395		T4	1
valid_sources[0x3c]	15686	1			T1	13		T2	400		T16	4
valid_sources[0x3d]	15087	1			T5	1		T1	9		T2	238
valid_sources[0x3e]	16121	1			T1	12		T2	253		T4	3
valid_sources[0x3f]	14413	1			T1	6		T2	337		T16	1
valid_sources[0x40]	16138	1			T1	10		T2	406		T4	5
valid_sources[0x41]	15753	1			T1	14		T2	352		T17	6
valid_sources[0x42]	15196	1			T1	11		T2	439		T4	6
valid_sources[0x43]	15784	1			T1	11		T2	343		T4	4
valid_sources[0x44]	15790	1			T1	11		T2	464		T20	3
valid_sources[0x45]	16275	1			T1	12		T2	296		T20	1
valid_sources[0x46]	15307	1			T1	8		T2	460		T18	1
valid_sources[0x47]	14199	1			T1	13		T2	395		T4	2
valid_sources[0x48]	15262	1			T1	8		T2	416		T19	3
valid_sources[0x49]	14248	1			T1	18		T2	377		T4	2
valid_sources[0x4a]	15692	1			T1	18		T2	386		T4	2
valid_sources[0x4b]	15512	1			T1	6		T2	349		T4	1
valid_sources[0x4c]	15620	1			T1	15		T2	420		T4	1
valid_sources[0x4d]	15005	1			T1	4		T2	301		T18	3
valid_sources[0x4e]	15339	1			T1	4		T2	399		T4	1
valid_sources[0x4f]	15629	1			T1	7		T2	374		T20	3
valid_sources[0x50]	15062	1			T1	9		T2	367		T4	2
valid_sources[0x51]	16994	1			T1	3		T2	312		T4	1
valid_sources[0x52]	14714	1			T5	1		T1	11		T2	356
valid_sources[0x53]	14405	1			T1	10		T2	414		T4	2
valid_sources[0x54]	15250	1			T1	13		T2	243		T4	2
valid_sources[0x55]	15853	1			T1	2		T2	426		T4	2
valid_sources[0x56]	14773	1			T5	1		T1	10		T2	423
valid_sources[0x57]	14608	1			T5	2		T1	6		T2	340
valid_sources[0x58]	16963	1			T1	5		T2	336		T4	2
valid_sources[0x59]	14233	1			T1	3		T2	368		T4	3
valid_sources[0x5a]	15099	1			T1	7		T2	340		T4	4
valid_sources[0x5b]	14900	1			T1	2		T2	347		T4	2
valid_sources[0x5c]	14991	1			T1	5		T2	402		T20	2
valid_sources[0x5d]	15769	1			T1	16		T2	307		T4	4
valid_sources[0x5e]	14654	1			T1	7		T2	375		T4	2
valid_sources[0x5f]	14997	1			T1	8		T2	379		T4	3
valid_sources[0x60]	14886	1			T1	5		T2	351		T4	1
valid_sources[0x61]	15270	1			T1	9		T2	421		T17	3
valid_sources[0x62]	15500	1			T1	14		T2	420		T17	32
valid_sources[0x63]	15081	1			T1	10		T2	318		T4	5
valid_sources[0x64]	15271	1			T1	8		T2	438		T4	5
valid_sources[0x65]	15929	1			T1	11		T2	329		T19	3
valid_sources[0x66]	16360	1			T1	6		T2	352		T18	1
valid_sources[0x67]	14414	1			T1	7		T2	277		T20	3
valid_sources[0x68]	16237	1			T5	1		T1	10		T2	337
valid_sources[0x69]	15840	1			T1	7		T2	398		T20	1
valid_sources[0x6a]	15565	1			T1	19		T2	335		T4	1
valid_sources[0x6b]	14777	1			T1	8		T2	357		T18	2
valid_sources[0x6c]	15122	1			T5	2		T1	12		T2	281
valid_sources[0x6d]	17070	1			T5	2		T1	3		T2	409
valid_sources[0x6e]	14469	1			T1	5		T2	271		T16	1
valid_sources[0x6f]	16527	1			T1	13		T2	426		T4	5
valid_sources[0x70]	13932	1			T1	8		T2	310		T4	3
valid_sources[0x71]	15313	1			T1	9		T2	322		T4	2
valid_sources[0x72]	15614	1			T1	8		T2	392		T20	1
valid_sources[0x73]	14582	1			T5	1		T1	11		T2	325
valid_sources[0x74]	15802	1			T6	1		T1	9		T2	408
valid_sources[0x75]	16015	1			T1	8		T2	462		T4	2
valid_sources[0x76]	15105	1			T1	9		T2	389		T18	1
valid_sources[0x77]	15387	1			T1	6		T2	410		T20	4
valid_sources[0x78]	15480	1			T6	1		T1	10		T2	331
valid_sources[0x79]	14968	1			T1	7		T2	269		T17	12
valid_sources[0x7a]	15621	1			T1	9		T2	388		T4	4
valid_sources[0x7b]	15965	1			T1	6		T2	425		T4	7
valid_sources[0x7c]	16380	1			T1	11		T2	314		T4	5
valid_sources[0x7d]	15060	1			T1	10		T2	346		T4	3
valid_sources[0x7e]	15962	1			T5	1		T1	3		T2	387
valid_sources[0x7f]	14957	1			T1	7		T2	418		T18	1
valid_sources[0x80]	17690	1			T1	10		T2	459		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

852060

1

T5

20

T6

4

T1

147

values[0x0]

all_enables

biggest_size

1281029

1

T5

6

T6

1

T1

577

values[0x1]

all_enables

biggest_size

1235356

1

T5

6

T1

332

T2

30355