Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	748580345	72621	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	748580345	72621	0	0
T1	2566120	142	0	0
T2	2331850	1890	0	0
T3	0	280	0	0
T4	255990	0	0	0
T9	0	62	0	0
T10	0	1094	0	0
T11	0	1386	0	0
T12	0	136	0	0
T13	0	833	0	0
T14	0	444	0	0
T15	0	72	0	0
T16	7725	0	0	0
T17	7000	0	0	0
T18	11895	0	0	0
T19	199410	0	0	0
T20	214930	0	0	0
T21	8910	0	0	0
T22	9695	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	149716069	10810	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149716069	10810	0	0
T1	513224	20	0	0
T2	466370	242	0	0
T3	0	45	0	0
T4	51198	0	0	0
T9	0	9	0	0
T10	0	144	0	0
T11	0	221	0	0
T12	0	20	0	0
T13	0	162	0	0
T14	0	71	0	0
T15	0	11	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	149716069	14615	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149716069	14615	0	0
T1	513224	28	0	0
T2	466370	377	0	0
T3	0	57	0	0
T4	51198	0	0	0
T9	0	12	0	0
T10	0	221	0	0
T11	0	281	0	0
T12	0	27	0	0
T13	0	162	0	0
T14	0	92	0	0
T15	0	14	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	149716069	22094	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149716069	22094	0	0
T1	513224	46	0	0
T2	466370	619	0	0
T3	0	78	0	0
T4	51198	0	0	0
T9	0	18	0	0
T10	0	365	0	0
T11	0	383	0	0
T12	0	42	0	0
T13	0	185	0	0
T14	0	122	0	0
T15	0	22	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	149716069	10526	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149716069	10526	0	0
T1	513224	20	0	0
T2	466370	273	0	0
T3	0	43	0	0
T4	51198	0	0	0
T9	0	9	0	0
T10	0	141	0	0
T11	0	220	0	0
T12	0	20	0	0
T13	0	162	0	0
T14	0	70	0	0
T15	0	10	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	149716069	14576	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149716069	14576	0	0
T1	513224	28	0	0
T2	466370	379	0	0
T3	0	57	0	0
T4	51198	0	0	0
T9	0	14	0	0
T10	0	223	0	0
T11	0	281	0	0
T12	0	27	0	0
T13	0	162	0	0
T14	0	89	0	0
T15	0	15	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0