Line Coverage for Module :
clkmgr_sec_cm_checker_assert
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 23 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
23 |
1 |
1 |
Cond Coverage for Module :
clkmgr_sec_cm_checker_assert
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (((!rst_ni)) || disable_sva)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
Assert Coverage for Module :
clkmgr_sec_cm_checker_assert
Assertion Details
AllClkBypReqFalse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
149716069 |
147159738 |
0 |
0 |
T1 |
513224 |
512226 |
0 |
0 |
T2 |
466370 |
460713 |
0 |
0 |
T4 |
51198 |
2985 |
0 |
0 |
T5 |
2316 |
1961 |
0 |
0 |
T6 |
1282 |
1211 |
0 |
0 |
T16 |
1545 |
1369 |
0 |
0 |
T17 |
1400 |
1386 |
0 |
0 |
T18 |
2379 |
2255 |
0 |
0 |
T19 |
39882 |
39823 |
0 |
0 |
T20 |
42986 |
42952 |
0 |
0 |
AllClkBypReqTrue_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
149716069 |
130556 |
0 |
0 |
T1 |
513224 |
109 |
0 |
0 |
T2 |
466370 |
2056 |
0 |
0 |
T3 |
0 |
3635 |
0 |
0 |
T4 |
51198 |
0 |
0 |
0 |
T5 |
2316 |
337 |
0 |
0 |
T6 |
1282 |
0 |
0 |
0 |
T10 |
0 |
1730 |
0 |
0 |
T16 |
1545 |
23 |
0 |
0 |
T17 |
1400 |
0 |
0 |
0 |
T18 |
2379 |
29 |
0 |
0 |
T19 |
39882 |
0 |
0 |
0 |
T20 |
42986 |
0 |
0 |
0 |
T104 |
0 |
43 |
0 |
0 |
T105 |
0 |
226 |
0 |
0 |
T106 |
0 |
174 |
0 |
0 |
IoClkBypReqFalse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
149716069 |
147079695 |
0 |
2415 |
T1 |
513224 |
512156 |
0 |
3 |
T2 |
466370 |
460640 |
0 |
3 |
T4 |
51198 |
2967 |
0 |
3 |
T5 |
2316 |
1777 |
0 |
3 |
T6 |
1282 |
1209 |
0 |
3 |
T16 |
1545 |
1293 |
0 |
3 |
T17 |
1400 |
1384 |
0 |
3 |
T18 |
2379 |
1861 |
0 |
3 |
T19 |
39882 |
39821 |
0 |
3 |
T20 |
42986 |
42950 |
0 |
3 |
IoClkBypReqTrue_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
149716069 |
206065 |
0 |
0 |
T1 |
513224 |
159 |
0 |
0 |
T2 |
466370 |
2769 |
0 |
0 |
T3 |
0 |
4387 |
0 |
0 |
T4 |
51198 |
0 |
0 |
0 |
T5 |
2316 |
519 |
0 |
0 |
T6 |
1282 |
0 |
0 |
0 |
T10 |
0 |
2021 |
0 |
0 |
T16 |
1545 |
97 |
0 |
0 |
T17 |
1400 |
0 |
0 |
0 |
T18 |
2379 |
421 |
0 |
0 |
T19 |
39882 |
0 |
0 |
0 |
T20 |
42986 |
0 |
0 |
0 |
T104 |
0 |
138 |
0 |
0 |
T105 |
0 |
409 |
0 |
0 |
T106 |
0 |
305 |
0 |
0 |
LcClkBypAckFalse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
149716069 |
147167968 |
0 |
0 |
T1 |
513224 |
512219 |
0 |
0 |
T2 |
466370 |
460710 |
0 |
0 |
T4 |
51198 |
2985 |
0 |
0 |
T5 |
2316 |
1962 |
0 |
0 |
T6 |
1282 |
1211 |
0 |
0 |
T16 |
1545 |
1392 |
0 |
0 |
T17 |
1400 |
1386 |
0 |
0 |
T18 |
2379 |
2035 |
0 |
0 |
T19 |
39882 |
39823 |
0 |
0 |
T20 |
42986 |
42952 |
0 |
0 |
LcClkBypAckTrue_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
149716069 |
122326 |
0 |
0 |
T1 |
513224 |
116 |
0 |
0 |
T2 |
466370 |
2091 |
0 |
0 |
T3 |
0 |
2714 |
0 |
0 |
T4 |
51198 |
0 |
0 |
0 |
T5 |
2316 |
336 |
0 |
0 |
T6 |
1282 |
0 |
0 |
0 |
T10 |
0 |
1417 |
0 |
0 |
T16 |
1545 |
0 |
0 |
0 |
T17 |
1400 |
0 |
0 |
0 |
T18 |
2379 |
249 |
0 |
0 |
T19 |
39882 |
0 |
0 |
0 |
T20 |
42986 |
0 |
0 |
0 |
T104 |
0 |
93 |
0 |
0 |
T105 |
0 |
261 |
0 |
0 |
T106 |
0 |
195 |
0 |
0 |
T107 |
0 |
26 |
0 |
0 |