Module Definition
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Module : clkmgr_sec_cm_checker_assert
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_sec_cm_checker_assert 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : clkmgr_sec_cm_checker_assert
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
23 1 1


Cond Coverage for Module : clkmgr_sec_cm_checker_assert
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT5,T6,T1
01Unreachable
10CoveredT1,T2,T4

Assert Coverage for Module : clkmgr_sec_cm_checker_assert
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllClkBypReqFalse_A 149716069 147159738 0 0
AllClkBypReqTrue_A 149716069 130556 0 0
IoClkBypReqFalse_A 149716069 147079695 0 2415
IoClkBypReqTrue_A 149716069 206065 0 0
LcClkBypAckFalse_A 149716069 147167968 0 0
LcClkBypAckTrue_A 149716069 122326 0 0


AllClkBypReqFalse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 149716069 147159738 0 0
T1 513224 512226 0 0
T2 466370 460713 0 0
T4 51198 2985 0 0
T5 2316 1961 0 0
T6 1282 1211 0 0
T16 1545 1369 0 0
T17 1400 1386 0 0
T18 2379 2255 0 0
T19 39882 39823 0 0
T20 42986 42952 0 0

AllClkBypReqTrue_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 149716069 130556 0 0
T1 513224 109 0 0
T2 466370 2056 0 0
T3 0 3635 0 0
T4 51198 0 0 0
T5 2316 337 0 0
T6 1282 0 0 0
T10 0 1730 0 0
T16 1545 23 0 0
T17 1400 0 0 0
T18 2379 29 0 0
T19 39882 0 0 0
T20 42986 0 0 0
T104 0 43 0 0
T105 0 226 0 0
T106 0 174 0 0

IoClkBypReqFalse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 149716069 147079695 0 2415
T1 513224 512156 0 3
T2 466370 460640 0 3
T4 51198 2967 0 3
T5 2316 1777 0 3
T6 1282 1209 0 3
T16 1545 1293 0 3
T17 1400 1384 0 3
T18 2379 1861 0 3
T19 39882 39821 0 3
T20 42986 42950 0 3

IoClkBypReqTrue_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 149716069 206065 0 0
T1 513224 159 0 0
T2 466370 2769 0 0
T3 0 4387 0 0
T4 51198 0 0 0
T5 2316 519 0 0
T6 1282 0 0 0
T10 0 2021 0 0
T16 1545 97 0 0
T17 1400 0 0 0
T18 2379 421 0 0
T19 39882 0 0 0
T20 42986 0 0 0
T104 0 138 0 0
T105 0 409 0 0
T106 0 305 0 0

LcClkBypAckFalse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 149716069 147167968 0 0
T1 513224 512219 0 0
T2 466370 460710 0 0
T4 51198 2985 0 0
T5 2316 1962 0 0
T6 1282 1211 0 0
T16 1545 1392 0 0
T17 1400 1386 0 0
T18 2379 2035 0 0
T19 39882 39823 0 0
T20 42986 42952 0 0

LcClkBypAckTrue_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 149716069 122326 0 0
T1 513224 116 0 0
T2 466370 2091 0 0
T3 0 2714 0 0
T4 51198 0 0 0
T5 2316 336 0 0
T6 1282 0 0 0
T10 0 1417 0 0
T16 1545 0 0 0
T17 1400 0 0 0
T18 2379 249 0 0
T19 39882 0 0 0
T20 42986 0 0 0
T104 0 93 0 0
T105 0 261 0 0
T106 0 195 0 0
T107 0 26 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%