Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1828298596	15318	0	0
TransStop_A	1828298596	7703	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1828298596	15318	0	0
T1	3985796	69	0	0
T2	1824680	402	0	0
T3	0	187	0	0
T4	204796	0	0	0
T6	10260	4	0	0
T10	0	220	0	0
T11	0	434	0	0
T12	0	4	0	0
T16	6304	0	0	0
T17	62224	4	0	0
T18	9916	0	0	0
T19	616716	0	0	0
T20	620464	0	0	0
T21	10976	0	0	0
T22	0	3	0	0
T108	0	16	0	0
T109	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1828298596	7703	0	0
T1	3985796	31	0	0
T2	1824680	222	0	0
T3	0	78	0	0
T4	204796	0	0	0
T6	10260	4	0	0
T10	0	107	0	0
T11	0	192	0	0
T12	0	4	0	0
T13	0	30	0	0
T16	6304	0	0	0
T17	62224	4	0	0
T18	9916	0	0	0
T19	616716	0	0	0
T20	620464	0	0	0
T21	10976	0	0	0
T22	0	1	0	0
T108	0	2	0	0
T109	0	26	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	457074649	3837	0	0
TransStop_A	457074649	1899	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074649	3837	0	0
T1	996449	17	0	0
T2	456170	99	0	0
T3	0	48	0	0
T4	51199	0	0	0
T6	2565	1	0	0
T10	0	55	0	0
T11	0	111	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15556	1	0	0
T18	2479	0	0	0
T19	154179	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T108	0	6	0	0
T109	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074649	1899	0	0
T1	996449	7	0	0
T2	456170	58	0	0
T3	0	22	0	0
T4	51199	0	0	0
T6	2565	1	0	0
T10	0	24	0	0
T11	0	45	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15556	1	0	0
T18	2479	0	0	0
T19	154179	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T108	0	1	0	0
T109	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	457074649	3877	0	0
TransStop_A	457074649	1929	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074649	3877	0	0
T1	996449	17	0	0
T2	456170	105	0	0
T3	0	48	0	0
T4	51199	0	0	0
T6	2565	1	0	0
T10	0	49	0	0
T11	0	93	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15556	1	0	0
T18	2479	0	0	0
T19	154179	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T22	0	1	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074649	1929	0	0
T1	996449	5	0	0
T2	456170	56	0	0
T3	0	15	0	0
T4	51199	0	0	0
T6	2565	1	0	0
T10	0	24	0	0
T11	0	44	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15556	1	0	0
T18	2479	0	0	0
T19	154179	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T22	0	1	0	0
T109	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	457074649	3818	0	0
TransStop_A	457074649	1951	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074649	3818	0	0
T1	996449	19	0	0
T2	456170	98	0	0
T3	0	48	0	0
T4	51199	0	0	0
T6	2565	1	0	0
T10	0	54	0	0
T11	0	114	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15556	1	0	0
T18	2479	0	0	0
T19	154179	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T22	0	1	0	0
T108	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074649	1951	0	0
T1	996449	11	0	0
T2	456170	53	0	0
T3	0	18	0	0
T4	51199	0	0	0
T6	2565	1	0	0
T10	0	28	0	0
T11	0	55	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15556	1	0	0
T18	2479	0	0	0
T19	154179	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T108	0	1	0	0
T109	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	457074649	3786	0	0
TransStop_A	457074649	1924	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074649	3786	0	0
T1	996449	16	0	0
T2	456170	100	0	0
T3	0	43	0	0
T4	51199	0	0	0
T6	2565	1	0	0
T10	0	62	0	0
T11	0	116	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15556	1	0	0
T18	2479	0	0	0
T19	154179	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T22	0	1	0	0
T108	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074649	1924	0	0
T1	996449	8	0	0
T2	456170	55	0	0
T3	0	23	0	0
T4	51199	0	0	0
T6	2565	1	0	0
T10	0	31	0	0
T11	0	48	0	0
T12	0	1	0	0
T13	0	30	0	0
T16	1576	0	0	0
T17	15556	1	0	0
T18	2479	0	0	0
T19	154179	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T109	0	8	0	0