Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	150656905	4924563	0	0
clk_enables_rd_A	150656905	42885	0	0
clk_hints_rd_A	150656905	37608	0	0
extclk_ctrl_rd_A	150656905	48950	0	0
extclk_ctrl_regwen_rd_A	150656905	36691	0	0
jitter_enable_rd_A	150656905	55228	0	0
jitter_regwen_rd_A	150656905	42089	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150656905	4924563	0	0
T2	466370	123825	0	0
T3	0	79902	0	0
T4	51198	0	0	0
T10	0	56998	0	0
T11	0	103420	0	0
T13	0	55365	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0
T23	116049	0	0	0
T32	0	139526	0	0
T70	0	28692	0	0
T71	0	69789	0	0
T72	0	55421	0	0
T73	0	132488	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150656905	42885	0	0
T2	466370	4607	0	0
T3	0	3237	0	0
T4	51198	0	0	0
T10	0	2406	0	0
T12	0	6	0	0
T13	0	2036	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0
T23	116049	0	0	0
T24	0	2	0	0
T25	0	18	0	0
T70	0	626	0	0
T135	0	1	0	0
T136	0	6	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150656905	37608	0	0
T2	466370	4139	0	0
T3	0	2910	0	0
T4	51198	0	0	0
T10	0	2084	0	0
T12	0	9	0	0
T13	0	1883	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0
T23	116049	0	0	0
T24	0	11	0	0
T25	0	6	0	0
T135	0	2	0	0
T137	0	3	0	0
T138	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150656905	48950	0	0
T1	513224	0	0	0
T2	466370	4814	0	0
T3	0	3664	0	0
T4	51198	0	0	0
T5	2316	71	0	0
T6	1282	0	0	0
T10	0	2501	0	0
T12	0	44	0	0
T13	0	2543	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T74	0	76	0	0
T104	0	18	0	0
T139	0	112	0	0
T140	0	6	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150656905	36691	0	0
T2	466370	3877	0	0
T3	0	2616	0	0
T4	51198	0	0	0
T10	0	2134	0	0
T13	0	1714	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0
T23	116049	0	0	0
T70	0	513	0	0
T74	0	37	0	0
T102	0	35	0	0
T103	0	37	0	0
T139	0	60	0	0
T141	0	50	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150656905	55228	0	0
T2	466370	5907	0	0
T3	0	3371	0	0
T4	51198	0	0	0
T10	0	2556	0	0
T12	0	110	0	0
T13	0	3211	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0
T23	116049	0	0	0
T24	0	227	0	0
T25	0	440	0	0
T135	0	229	0	0
T137	0	67	0	0
T138	0	117	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150656905	42089	0	0
T2	466370	4546	0	0
T3	0	3202	0	0
T4	51198	0	0	0
T10	0	2371	0	0
T13	0	2125	0	0
T16	1545	0	0	0
T17	1400	0	0	0
T18	2379	0	0	0
T19	39882	0	0	0
T20	42986	0	0	0
T21	1782	0	0	0
T22	1939	0	0	0
T23	116049	0	0	0
T33	0	4918	0	0
T55	0	1667	0	0
T70	0	640	0	0
T71	0	2689	0	0
T72	0	2161	0	0
T142	0	2173	0	0