Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48639	0	0
CgEnOn_A	2147483647	39570	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48639	0	0
T1	2478639	49	0	0
T2	1162508	289	0	0
T3	0	48	0	0
T4	119112	27	0	0
T5	17980	3	0	0
T6	6802	4	0	0
T16	4238	3	0	0
T17	41618	7	0	0
T18	6819	3	0	0
T19	403040	3	0	0
T20	405542	3	0	0
T21	2744	0	0	0
T30	3905	0	0	0
T31	3326	0	0	0
T34	17954	15	0	0
T35	0	20	0	0
T36	0	5	0	0
T53	0	15	0	0
T139	167166	0	0	0
T143	0	20	0	0
T144	0	20	0	0
T145	0	5	0	0
T146	0	10	0	0
T147	0	15	0	0
T148	0	15	0	0
T149	5635	0	0	0
T150	3696	0	0	0
T151	13292	0	0	0
T152	341491	0	0	0
T153	11024	0	0	0
T154	10903	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39570	0	0
T1	423378	19	0	0
T2	301646	256	0	0
T3	0	237	0	0
T4	18765	0	0	0
T6	0	1	0	0
T10	0	223	0	0
T11	0	802	0	0
T12	0	4	0	0
T16	1150	0	0	0
T17	11130	4	0	0
T18	1961	0	0	0
T19	106615	0	0	0
T20	107280	0	0	0
T21	1926	46	0	0
T22	1368	0	0	0
T23	15753	0	0	0
T30	1266	0	0	0
T31	1096	0	0	0
T34	5949	24	0	0
T35	0	20	0	0
T36	0	5	0	0
T53	0	15	0	0
T139	39874	0	0	0
T143	0	20	0	0
T144	0	20	0	0
T145	0	5	0	0
T146	0	10	0	0
T147	0	15	0	0
T148	0	15	0	0
T149	1838	0	0	0
T150	1215	9	0	0
T151	4478	0	0	0
T152	113790	0	0	0
T153	4334	0	0	0
T154	3619	0	0	0
T155	0	22	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	213715853	168	0	0
CgEnOn_A	213715853	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213715853	168	0	0
T30	844	0	0	0
T31	731	0	0	0
T34	3966	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T53	0	3	0	0
T139	26584	0	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	1225	0	0	0
T150	810	0	0	0
T151	2986	0	0	0
T152	75860	0	0	0
T153	2890	0	0	0
T154	2413	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213715853	168	0	0
T30	844	0	0	0
T31	731	0	0	0
T34	3966	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T53	0	3	0	0
T139	26584	0	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	1225	0	0	0
T150	810	0	0	0
T151	2986	0	0	0
T152	75860	0	0	0
T153	2890	0	0	0
T154	2413	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	106857308	168	0	0
CgEnOn_A	106857308	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106857308	168	0	0
T30	422	0	0	0
T31	365	0	0	0
T34	1983	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T53	0	3	0	0
T139	13290	0	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	613	0	0	0
T150	405	0	0	0
T151	1492	0	0	0
T152	37930	0	0	0
T153	1444	0	0	0
T154	1206	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106857308	168	0	0
T30	422	0	0	0
T31	365	0	0	0
T34	1983	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T53	0	3	0	0
T139	13290	0	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	613	0	0	0
T150	405	0	0	0
T151	1492	0	0	0
T152	37930	0	0	0
T153	1444	0	0	0
T154	1206	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	428957267	168	0	0
CgEnOn_A	428957267	165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428957267	168	0	0
T30	1795	0	0	0
T31	1500	0	0	0
T34	8039	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T53	0	3	0	0
T139	100712	0	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	2571	0	0	0
T150	1671	0	0	0
T151	5830	0	0	0
T152	151841	0	0	0
T153	3802	0	0	0
T154	4872	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428957267	165	0	0
T30	1795	0	0	0
T31	1500	0	0	0
T34	8039	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T53	0	3	0	0
T139	100712	0	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	2571	0	0	0
T150	1671	0	0	0
T151	5830	0	0	0
T152	151841	0	0	0
T153	3802	0	0	0
T154	4872	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457074211	147	0	0
CgEnOn_A	457074211	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	147	0	0
T30	1871	0	0	0
T31	1561	0	0	0
T34	8829	1	0	0
T35	0	3	0	0
T36	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T139	104911	0	0	0
T143	0	5	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T149	2679	0	0	0
T150	1740	0	0	0
T151	6072	0	0	0
T152	194172	0	0	0
T153	3960	0	0	0
T154	5076	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	144	0	0
T30	1871	0	0	0
T31	1561	0	0	0
T34	8829	1	0	0
T35	0	3	0	0
T36	0	1	0	0
T53	0	2	0	0
T139	104911	0	0	0
T143	0	5	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	3	0	0
T149	2679	0	0	0
T150	1740	0	0	0
T151	6072	0	0	0
T152	194172	0	0	0
T153	3960	0	0	0
T154	5076	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	106857308	168	0	0
CgEnOn_A	106857308	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106857308	168	0	0
T30	422	0	0	0
T31	365	0	0	0
T34	1983	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T53	0	3	0	0
T139	13290	0	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	613	0	0	0
T150	405	0	0	0
T151	1492	0	0	0
T152	37930	0	0	0
T153	1444	0	0	0
T154	1206	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106857308	168	0	0
T30	422	0	0	0
T31	365	0	0	0
T34	1983	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T53	0	3	0	0
T139	13290	0	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	613	0	0	0
T150	405	0	0	0
T151	1492	0	0	0
T152	37930	0	0	0
T153	1444	0	0	0
T154	1206	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457074211	147	0	0
CgEnOn_A	457074211	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	147	0	0
T30	1871	0	0	0
T31	1561	0	0	0
T34	8829	1	0	0
T35	0	3	0	0
T36	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T139	104911	0	0	0
T143	0	5	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T149	2679	0	0	0
T150	1740	0	0	0
T151	6072	0	0	0
T152	194172	0	0	0
T153	3960	0	0	0
T154	5076	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	144	0	0
T30	1871	0	0	0
T31	1561	0	0	0
T34	8829	1	0	0
T35	0	3	0	0
T36	0	1	0	0
T53	0	2	0	0
T139	104911	0	0	0
T143	0	5	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	3	0	0
T149	2679	0	0	0
T150	1740	0	0	0
T151	6072	0	0	0
T152	194172	0	0	0
T153	3960	0	0	0
T154	5076	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	106857308	168	0	0
CgEnOn_A	106857308	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106857308	168	0	0
T30	422	0	0	0
T31	365	0	0	0
T34	1983	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T53	0	3	0	0
T139	13290	0	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	613	0	0	0
T150	405	0	0	0
T151	1492	0	0	0
T152	37930	0	0	0
T153	1444	0	0	0
T154	1206	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106857308	168	0	0
T30	422	0	0	0
T31	365	0	0	0
T34	1983	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T53	0	3	0	0
T139	13290	0	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	613	0	0	0
T150	405	0	0	0
T151	1492	0	0	0
T152	37930	0	0	0
T153	1444	0	0	0
T154	1206	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	213715853	7892	0	0
CgEnOn_A	213715853	5632	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213715853	7892	0	0
T1	423378	11	0	0
T2	201098	59	0	0
T4	12510	9	0	0
T5	5811	1	0	0
T6	1184	1	0	0
T16	767	1	0	0
T17	7420	2	0	0
T18	1308	1	0	0
T19	71077	1	0	0
T20	71520	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213715853	5632	0	0
T1	423378	1	0	0
T2	201098	48	0	0
T3	0	58	0	0
T4	12510	0	0	0
T10	0	54	0	0
T11	0	224	0	0
T12	0	1	0	0
T16	767	0	0	0
T17	7420	1	0	0
T18	1308	0	0	0
T19	71077	0	0	0
T20	71520	0	0	0
T21	1284	16	0	0
T22	912	0	0	0
T34	0	3	0	0
T155	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	106857308	7882	0	0
CgEnOn_A	106857308	5622	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106857308	7882	0	0
T1	211688	10	0	0
T2	100548	68	0	0
T4	6255	9	0	0
T5	2904	1	0	0
T6	592	1	0	0
T16	383	1	0	0
T17	3710	2	0	0
T18	653	1	0	0
T19	35538	1	0	0
T20	35760	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106857308	5622	0	0
T2	100548	57	0	0
T3	0	65	0	0
T4	6255	0	0	0
T10	0	58	0	0
T11	0	234	0	0
T12	0	1	0	0
T16	383	0	0	0
T17	3710	1	0	0
T18	653	0	0	0
T19	35538	0	0	0
T20	35760	0	0	0
T21	642	15	0	0
T22	456	0	0	0
T23	15753	0	0	0
T34	0	3	0	0
T150	0	9	0	0
T155	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	428957267	7923	0	0
CgEnOn_A	428957267	5660	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428957267	7923	0	0
T1	847125	11	0	0
T2	404692	63	0	0
T4	49149	9	0	0
T5	9265	1	0	0
T6	2462	1	0	0
T16	1512	1	0	0
T17	14933	2	0	0
T18	2379	1	0	0
T19	142247	1	0	0
T20	143146	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428957267	5660	0	0
T1	847125	1	0	0
T2	404692	52	0	0
T3	0	66	0	0
T4	49149	0	0	0
T10	0	56	0	0
T11	0	233	0	0
T12	0	1	0	0
T16	1512	0	0	0
T17	14933	1	0	0
T18	2379	0	0	0
T19	142247	0	0	0
T20	143146	0	0	0
T21	2633	15	0	0
T22	1862	0	0	0
T34	0	3	0	0
T155	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	219349740	7902	0	0
CgEnOn_A	219349740	5637	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219349740	7902	0	0
T1	481183	11	0	0
T2	216438	62	0	0
T4	24575	9	0	0
T5	4633	1	0	0
T6	1230	1	0	0
T16	756	1	0	0
T17	7467	2	0	0
T18	1189	1	0	0
T19	74007	1	0	0
T20	77336	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219349740	5637	0	0
T1	481183	1	0	0
T2	216438	52	0	0
T3	0	68	0	0
T4	24575	0	0	0
T10	0	56	0	0
T11	0	225	0	0
T12	0	1	0	0
T16	756	0	0	0
T17	7467	1	0	0
T18	1189	0	0	0
T19	74007	0	0	0
T20	77336	0	0	0
T21	1316	12	0	0
T22	931	0	0	0
T34	0	1	0	0
T155	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457074211	3984	0	0
CgEnOn_A	457074211	3981	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	3984	0	0
T1	996448	17	0	0
T2	456170	99	0	0
T3	0	48	0	0
T4	51198	0	0	0
T6	2564	1	0	0
T10	0	55	0	0
T11	0	111	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15555	1	0	0
T18	2479	0	0	0
T19	154178	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T108	0	6	0	0
T109	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	3981	0	0
T1	996448	17	0	0
T2	456170	99	0	0
T3	0	48	0	0
T4	51198	0	0	0
T6	2564	1	0	0
T10	0	55	0	0
T11	0	111	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15555	1	0	0
T18	2479	0	0	0
T19	154178	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T108	0	6	0	0
T109	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457074211	4024	0	0
CgEnOn_A	457074211	4021	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	4024	0	0
T1	996448	17	0	0
T2	456170	105	0	0
T3	0	48	0	0
T4	51198	0	0	0
T6	2564	1	0	0
T10	0	49	0	0
T11	0	93	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15555	1	0	0
T18	2479	0	0	0
T19	154178	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T22	0	1	0	0
T108	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	4021	0	0
T1	996448	17	0	0
T2	456170	105	0	0
T3	0	48	0	0
T4	51198	0	0	0
T6	2564	1	0	0
T10	0	49	0	0
T11	0	93	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15555	1	0	0
T18	2479	0	0	0
T19	154178	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T22	0	1	0	0
T108	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457074211	3965	0	0
CgEnOn_A	457074211	3962	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	3965	0	0
T1	996448	19	0	0
T2	456170	98	0	0
T3	0	48	0	0
T4	51198	0	0	0
T6	2564	1	0	0
T10	0	54	0	0
T11	0	114	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15555	1	0	0
T18	2479	0	0	0
T19	154178	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T22	0	1	0	0
T108	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	3962	0	0
T1	996448	19	0	0
T2	456170	98	0	0
T3	0	48	0	0
T4	51198	0	0	0
T6	2564	1	0	0
T10	0	54	0	0
T11	0	114	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15555	1	0	0
T18	2479	0	0	0
T19	154178	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T22	0	1	0	0
T108	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457074211	3933	0	0
CgEnOn_A	457074211	3930	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	3933	0	0
T1	996448	16	0	0
T2	456170	100	0	0
T3	0	43	0	0
T4	51198	0	0	0
T6	2564	1	0	0
T10	0	62	0	0
T11	0	116	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15555	1	0	0
T18	2479	0	0	0
T19	154178	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T22	0	1	0	0
T108	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457074211	3930	0	0
T1	996448	16	0	0
T2	456170	100	0	0
T3	0	43	0	0
T4	51198	0	0	0
T6	2564	1	0	0
T10	0	62	0	0
T11	0	116	0	0
T12	0	1	0	0
T16	1576	0	0	0
T17	15555	1	0	0
T18	2479	0	0	0
T19	154178	0	0	0
T20	155116	0	0	0
T21	2744	0	0	0
T22	0	1	0	0
T108	0	4	0	0