Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T2,T21,T3
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T34,T35,T36
1	1	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	968881797	14777	0	0
GateOpen_A	968881797	14777	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968881797	14777	0	0
T1	1963375	4	0	0
T2	922776	135	0	0
T3	0	138	0	0
T4	92492	0	0	0
T10	0	160	0	0
T11	0	614	0	0
T12	0	4	0	0
T16	3421	0	0	0
T17	33530	4	0	0
T18	5532	0	0	0
T19	322870	0	0	0
T20	327763	0	0	0
T21	5877	42	0	0
T22	4161	0	0	0
T34	0	10	0	0
T155	0	23	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	968881797	14777	0	0
T1	1963375	4	0	0
T2	922776	135	0	0
T3	0	138	0	0
T4	92492	0	0	0
T10	0	160	0	0
T11	0	614	0	0
T12	0	4	0	0
T16	3421	0	0	0
T17	33530	4	0	0
T18	5532	0	0	0
T19	322870	0	0	0
T20	327763	0	0	0
T21	5877	42	0	0
T22	4161	0	0	0
T34	0	10	0	0
T155	0	23	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T2,T21,T3
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T34,T35,T36
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	106857693	3662	0	0
GateOpen_A	106857693	3662	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106857693	3662	0	0
T1	211688	1	0	0
T2	100548	36	0	0
T3	0	36	0	0
T4	6256	0	0	0
T10	0	42	0	0
T11	0	156	0	0
T12	0	1	0	0
T16	384	0	0	0
T17	3710	1	0	0
T18	654	0	0	0
T19	35539	0	0	0
T20	35760	0	0	0
T21	642	11	0	0
T22	456	0	0	0
T34	0	3	0	0
T155	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106857693	3662	0	0
T1	211688	1	0	0
T2	100548	36	0	0
T3	0	36	0	0
T4	6256	0	0	0
T10	0	42	0	0
T11	0	156	0	0
T12	0	1	0	0
T16	384	0	0	0
T17	3710	1	0	0
T18	654	0	0	0
T19	35539	0	0	0
T20	35760	0	0	0
T21	642	11	0	0
T22	456	0	0	0
T34	0	3	0	0
T155	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T2,T21,T3
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T34,T35,T36
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	213716247	3688	0	0
GateOpen_A	213716247	3688	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213716247	3688	0	0
T1	423378	1	0	0
T2	201098	32	0	0
T3	0	30	0	0
T4	12511	0	0	0
T10	0	40	0	0
T11	0	152	0	0
T12	0	1	0	0
T16	768	0	0	0
T17	7420	1	0	0
T18	1309	0	0	0
T19	71077	0	0	0
T20	71520	0	0	0
T21	1284	12	0	0
T22	912	0	0	0
T34	0	3	0	0
T155	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213716247	3688	0	0
T1	423378	1	0	0
T2	201098	32	0	0
T3	0	30	0	0
T4	12511	0	0	0
T10	0	40	0	0
T11	0	152	0	0
T12	0	1	0	0
T16	768	0	0	0
T17	7420	1	0	0
T18	1309	0	0	0
T19	71077	0	0	0
T20	71520	0	0	0
T21	1284	12	0	0
T22	912	0	0	0
T34	0	3	0	0
T155	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T2,T21,T3
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T34,T35,T36
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	428957703	3708	0	0
GateOpen_A	428957703	3708	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428957703	3708	0	0
T1	847125	1	0	0
T2	404692	32	0	0
T3	0	34	0	0
T4	49149	0	0	0
T10	0	39	0	0
T11	0	156	0	0
T12	0	1	0	0
T16	1513	0	0	0
T17	14933	1	0	0
T18	2380	0	0	0
T19	142247	0	0	0
T20	143146	0	0	0
T21	2634	10	0	0
T22	1862	0	0	0
T34	0	3	0	0
T155	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428957703	3708	0	0
T1	847125	1	0	0
T2	404692	32	0	0
T3	0	34	0	0
T4	49149	0	0	0
T10	0	39	0	0
T11	0	156	0	0
T12	0	1	0	0
T16	1513	0	0	0
T17	14933	1	0	0
T18	2380	0	0	0
T19	142247	0	0	0
T20	143146	0	0	0
T21	2634	10	0	0
T22	1862	0	0	0
T34	0	3	0	0
T155	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T2,T21,T3
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T34,T35,T36
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	219350154	3719	0	0
GateOpen_A	219350154	3719	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219350154	3719	0	0
T1	481184	1	0	0
T2	216438	35	0	0
T3	0	38	0	0
T4	24576	0	0	0
T10	0	39	0	0
T11	0	150	0	0
T12	0	1	0	0
T16	756	0	0	0
T17	7467	1	0	0
T18	1189	0	0	0
T19	74007	0	0	0
T20	77337	0	0	0
T21	1317	9	0	0
T22	931	0	0	0
T34	0	1	0	0
T155	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219350154	3719	0	0
T1	481184	1	0	0
T2	216438	35	0	0
T3	0	38	0	0
T4	24576	0	0	0
T10	0	39	0	0
T11	0	150	0	0
T12	0	1	0	0
T16	756	0	0	0
T17	7467	1	0	0
T18	1189	0	0	0
T19	74007	0	0	0
T20	77337	0	0	0
T21	1317	9	0	0
T22	931	0	0	0
T34	0	1	0	0
T155	0	6	0	0