Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	621776	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3559105

1

T6

65

T1

78468

T17

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1029759	1			T6	72		T1	20900		T17	15
values[0x0]	1449002	1			T6	35		T1	31380		T17	18
values[0x1]	1702120	1			T6	34		T1	36964		T17	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	344693	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3836188

1

T6

86

T1

83883

T17

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15693	1			T1	334		T5	1		T2	4
valid_sources[0x01]	16263	1			T1	348		T2	1		T3	3
valid_sources[0x02]	17130	1			T1	378		T17	1		T19	4
valid_sources[0x03]	17104	1			T1	474		T19	4		T5	2
valid_sources[0x04]	14937	1			T6	1		T1	545		T5	1
valid_sources[0x05]	15201	1			T1	454		T5	2		T2	6
valid_sources[0x06]	15766	1			T1	50		T5	4		T2	4
valid_sources[0x07]	16822	1			T6	1		T1	380		T5	3
valid_sources[0x08]	15901	1			T1	299		T2	10		T26	4
valid_sources[0x09]	15149	1			T1	346		T17	1		T5	4
valid_sources[0x0a]	17968	1			T6	1		T1	592		T22	10
valid_sources[0x0b]	16377	1			T6	1		T1	451		T5	2
valid_sources[0x0c]	16901	1			T6	2		T1	453		T5	1
valid_sources[0x0d]	14793	1			T1	239		T19	2		T5	1
valid_sources[0x0e]	14639	1			T6	2		T1	424		T38	1
valid_sources[0x0f]	16151	1			T1	345		T2	12		T38	1
valid_sources[0x10]	15655	1			T6	1		T1	365		T5	2
valid_sources[0x11]	16598	1			T1	389		T19	3		T5	1
valid_sources[0x12]	16188	1			T6	1		T1	286		T2	5
valid_sources[0x13]	16542	1			T1	386		T5	1		T38	1
valid_sources[0x14]	15989	1			T6	1		T1	148		T2	6
valid_sources[0x15]	17087	1			T6	1		T1	380		T2	1
valid_sources[0x16]	15540	1			T6	3		T1	209		T2	8
valid_sources[0x17]	15787	1			T1	184		T5	2		T2	3
valid_sources[0x18]	16274	1			T1	437		T5	2		T2	7
valid_sources[0x19]	15740	1			T6	2		T1	161		T5	2
valid_sources[0x1a]	16638	1			T6	1		T1	580		T17	1
valid_sources[0x1b]	16731	1			T1	898		T5	1		T2	4
valid_sources[0x1c]	15104	1			T1	274		T2	7		T38	2
valid_sources[0x1d]	16989	1			T6	1		T1	342		T5	3
valid_sources[0x1e]	16082	1			T6	1		T1	767		T5	2
valid_sources[0x1f]	16694	1			T1	401		T5	1		T2	7
valid_sources[0x20]	16127	1			T1	160		T5	1		T2	11
valid_sources[0x21]	17380	1			T1	541		T5	1		T2	6
valid_sources[0x22]	17832	1			T1	506		T5	3		T3	3
valid_sources[0x23]	16710	1			T6	2		T1	277		T5	1
valid_sources[0x24]	16122	1			T1	242		T5	2		T2	4
valid_sources[0x25]	16845	1			T1	688		T2	5		T76	2
valid_sources[0x26]	17458	1			T1	216		T5	1		T2	8
valid_sources[0x27]	16294	1			T1	421		T2	7		T3	2
valid_sources[0x28]	16347	1			T1	272		T5	1		T2	3
valid_sources[0x29]	15892	1			T1	528		T17	1		T19	7
valid_sources[0x2a]	15559	1			T6	1		T1	435		T19	1
valid_sources[0x2b]	15244	1			T1	374		T5	2		T2	1
valid_sources[0x2c]	16820	1			T1	508		T19	4		T2	8
valid_sources[0x2d]	15559	1			T6	2		T1	411		T5	1
valid_sources[0x2e]	15736	1			T1	373		T19	1		T5	2
valid_sources[0x2f]	15753	1			T1	571		T5	1		T2	4
valid_sources[0x30]	16888	1			T1	323		T5	1		T2	4
valid_sources[0x31]	15706	1			T1	109		T21	2		T2	3
valid_sources[0x32]	17676	1			T6	2		T1	423		T5	1
valid_sources[0x33]	15763	1			T1	342		T2	4		T38	1
valid_sources[0x34]	15534	1			T6	2		T1	182		T17	1
valid_sources[0x35]	16645	1			T1	411		T19	4		T22	1
valid_sources[0x36]	15617	1			T1	19		T17	1		T5	3
valid_sources[0x37]	16924	1			T1	487		T2	4		T11	2
valid_sources[0x38]	16370	1			T6	1		T1	113		T5	2
valid_sources[0x39]	16830	1			T1	161		T5	2		T2	8
valid_sources[0x3a]	15506	1			T1	159		T2	1		T26	1
valid_sources[0x3b]	16357	1			T1	418		T2	4		T3	1
valid_sources[0x3c]	16571	1			T1	135		T2	7		T26	6
valid_sources[0x3d]	16413	1			T6	1		T1	577		T38	2
valid_sources[0x3e]	17513	1			T1	734		T5	1		T2	5
valid_sources[0x3f]	17609	1			T1	257		T2	5		T26	2
valid_sources[0x40]	15661	1			T1	700		T5	1		T2	3
valid_sources[0x41]	16988	1			T1	158		T17	1		T5	1
valid_sources[0x42]	16354	1			T6	1		T1	563		T5	2
valid_sources[0x43]	16618	1			T1	345		T5	1		T2	12
valid_sources[0x44]	16242	1			T6	2		T1	387		T19	9
valid_sources[0x45]	15571	1			T1	585		T2	7		T3	3
valid_sources[0x46]	16652	1			T6	1		T1	186		T2	8
valid_sources[0x47]	15662	1			T6	2		T1	408		T21	2
valid_sources[0x48]	15381	1			T1	561		T17	3		T18	10
valid_sources[0x49]	16400	1			T1	328		T5	1		T2	3
valid_sources[0x4a]	15388	1			T6	3		T1	256		T18	4
valid_sources[0x4b]	16326	1			T1	511		T17	1		T19	1
valid_sources[0x4c]	17505	1			T1	853		T17	1		T2	5
valid_sources[0x4d]	16262	1			T1	395		T5	2		T2	6
valid_sources[0x4e]	16676	1			T1	339		T5	1		T2	2
valid_sources[0x4f]	17307	1			T1	509		T2	12		T26	1
valid_sources[0x50]	16303	1			T1	533		T5	2		T2	4
valid_sources[0x51]	14712	1			T1	689		T2	6		T26	2
valid_sources[0x52]	16847	1			T6	1		T1	91		T5	3
valid_sources[0x53]	15954	1			T1	308		T5	1		T22	34
valid_sources[0x54]	17121	1			T6	1		T1	585		T19	1
valid_sources[0x55]	15575	1			T1	273		T2	2		T3	9
valid_sources[0x56]	16692	1			T1	323		T20	1		T5	1
valid_sources[0x57]	15900	1			T1	250		T2	12		T3	6
valid_sources[0x58]	16225	1			T1	196		T2	1		T3	3
valid_sources[0x59]	15662	1			T1	142		T5	1		T2	6
valid_sources[0x5a]	16558	1			T6	3		T1	110		T21	3
valid_sources[0x5b]	15970	1			T1	212		T17	2		T19	5
valid_sources[0x5c]	16860	1			T1	561		T2	4		T64	1
valid_sources[0x5d]	15405	1			T6	1		T1	146		T2	12
valid_sources[0x5e]	16389	1			T1	74		T38	1		T26	3
valid_sources[0x5f]	17605	1			T1	618		T2	4		T64	1
valid_sources[0x60]	15362	1			T6	3		T1	325		T5	1
valid_sources[0x61]	15902	1			T1	119		T5	3		T38	1
valid_sources[0x62]	16951	1			T6	1		T1	413		T17	1
valid_sources[0x63]	17837	1			T1	567		T5	1		T2	9
valid_sources[0x64]	16134	1			T6	1		T1	331		T19	3
valid_sources[0x65]	16871	1			T6	1		T1	457		T26	1
valid_sources[0x66]	16414	1			T1	451		T19	1		T5	1
valid_sources[0x67]	16111	1			T1	269		T2	3		T38	1
valid_sources[0x68]	15679	1			T1	210		T5	1		T2	9
valid_sources[0x69]	17680	1			T1	26		T17	2		T2	5
valid_sources[0x6a]	16124	1			T1	575		T17	2		T2	7
valid_sources[0x6b]	16780	1			T1	367		T2	11		T38	1
valid_sources[0x6c]	16424	1			T6	1		T1	187		T17	2
valid_sources[0x6d]	15287	1			T1	264		T5	2		T2	12
valid_sources[0x6e]	15911	1			T1	69		T18	1		T5	5
valid_sources[0x6f]	16515	1			T6	2		T1	344		T2	7
valid_sources[0x70]	16684	1			T6	1		T1	393		T2	7
valid_sources[0x71]	15638	1			T6	2		T1	555		T19	2
valid_sources[0x72]	15979	1			T6	1		T1	481		T21	2
valid_sources[0x73]	16205	1			T1	325		T2	5		T26	4
valid_sources[0x74]	15925	1			T1	38		T19	5		T2	6
valid_sources[0x75]	16629	1			T1	238		T5	1		T2	6
valid_sources[0x76]	15841	1			T1	531		T2	1		T3	3
valid_sources[0x77]	16701	1			T1	376		T2	1		T64	1
valid_sources[0x78]	16383	1			T6	1		T1	140		T2	5
valid_sources[0x79]	15986	1			T6	2		T1	512		T2	5
valid_sources[0x7a]	16335	1			T6	2		T1	390		T2	4
valid_sources[0x7b]	16729	1			T6	1		T1	495		T2	3
valid_sources[0x7c]	16482	1			T1	55		T18	2		T20	1
valid_sources[0x7d]	15270	1			T1	150		T2	11		T76	1
valid_sources[0x7e]	15136	1			T6	4		T1	299		T2	4
valid_sources[0x7f]	17944	1			T1	468		T5	1		T2	3
valid_sources[0x80]	16513	1			T1	335		T5	2		T2	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

898971

1

T6

31

T1

19257

T17

8

values[0x0]

all_enables

biggest_size

1353512

1

T6

23

T1

29983

T17

3

values[0x1]

all_enables

biggest_size

1306622

1

T6

11

T1

29228

T17

1