Group : clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg
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Group : clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
PeriDiv2 100.00 1 100 1 64 64
PeriDiv4 100.00 1 100 1 64 64
PeriIo 100.00 1 100 1 64 64
PeriUsb 100.00 1 100 1 64 64




Group Instance : PeriDiv2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriDiv2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriDiv2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriDiv2
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0



Group Instance : PeriDiv4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriDiv4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriDiv4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriDiv4
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0



Group Instance : PeriIo
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriIo

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriIo
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriIo
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0



Group Instance : PeriUsb
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriUsb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriUsb
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriUsb
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 350685 1 T6 8 T1 235 T7 2
auto[1] 297114522 1 T6 4535 T1 454694 T7 4825



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8870 1 T6 8 T1 12 T7 108
auto[1] 297456337 1 T6 4535 T1 454716 T7 4719



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 168911562 1 T6 4519 T1 247972 T7 4827
auto[1] 128553645 1 T6 24 T1 206745 T17 900



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5472 1 T6 6 T1 6 T7 2
auto[0] auto[0] auto[1] 1566 1 T6 2 T1 6 T17 2
auto[0] auto[1] auto[0] 241135 1 T1 115 T21 36 T2 210
auto[0] auto[1] auto[1] 102512 1 T1 108 T21 194 T2 131
auto[1] auto[1] auto[0] 168663123 1 T6 4513 T1 247960 T7 4719
auto[1] auto[1] auto[1] 128449567 1 T6 22 T1 206733 T17 898


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 182900 1 T6 8 T1 119 T7 2
auto[1] 148547763 1 T6 2263 T1 227345 T7 2412



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7955 1 T6 8 T1 12 T7 55
auto[1] 148722708 1 T6 2263 T1 227356 T7 2359



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 84453791 1 T6 2259 T1 123984 T7 2414
auto[1] 64276872 1 T6 12 T1 103372 T17 451



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5472 1 T6 6 T1 6 T7 2
auto[0] auto[0] auto[1] 1566 1 T6 2 T1 6 T17 2
auto[0] auto[1] auto[0] 124550 1 T1 54 T21 42 T2 93
auto[0] auto[1] auto[1] 51312 1 T1 53 T21 62 T2 82
auto[1] auto[1] auto[0] 84322852 1 T6 2253 T1 123978 T7 2359
auto[1] auto[1] auto[1] 64223994 1 T6 10 T1 103366 T17 449


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 718820 1 T6 8 T1 447 T7 2
auto[1] 593360098 1 T6 9075 T1 908933 T7 9653



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10688 1 T6 8 T1 12 T7 213
auto[1] 594068230 1 T6 9075 T1 908977 T7 9442



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 336971651 1 T6 9035 T1 495488 T7 9655
auto[1] 257107267 1 T6 48 T1 413490 T17 1802



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5472 1 T6 6 T1 6 T7 2
auto[0] auto[0] auto[1] 1566 1 T6 2 T1 6 T17 2
auto[0] auto[1] auto[0] 511323 1 T1 220 T21 173 T2 376
auto[0] auto[1] auto[1] 200459 1 T1 215 T21 303 T2 350
auto[1] auto[1] auto[0] 336451206 1 T6 9029 T1 495465 T7 9442
auto[1] auto[1] auto[1] 256905242 1 T6 46 T1 413467 T17 1800


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 371405 1 T6 8 T1 232 T7 2
auto[1] 301828944 1 T6 4533 T1 473207 T7 5911



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8833 1 T6 8 T1 12 T7 165
auto[1] 302191516 1 T6 4533 T1 473229 T7 5748



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 171389955 1 T6 4517 T1 258699 T7 5913
auto[1] 130810394 1 T6 24 T1 214531 T17 900



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5452 1 T6 6 T1 6 T7 2
auto[0] auto[0] auto[1] 1586 1 T6 2 T1 6 T17 2
auto[0] auto[1] auto[0] 262198 1 T1 104 T21 86 T2 232
auto[0] auto[1] auto[1] 102169 1 T1 116 T21 138 T2 104
auto[1] auto[1] auto[0] 171120510 1 T6 4511 T1 258688 T7 5748
auto[1] auto[1] auto[1] 130706639 1 T6 22 T1 214518 T17 898


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded

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