Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	787734250	72277	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787734250	72277	0	0
T1	1154765	289	0	0
T2	0	228	0	0
T3	0	73	0	0
T4	70680	0	0	0
T5	150225	0	0	0
T7	3540	0	0	0
T10	0	45	0	0
T11	0	280	0	0
T12	0	528	0	0
T13	0	656	0	0
T14	0	124	0	0
T15	0	450	0	0
T16	0	267	0	0
T17	8110	0	0	0
T18	11130	0	0	0
T19	12525	0	0	0
T20	7345	0	0	0
T21	4520	0	0	0
T22	7640	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157546850	10893	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	10893	0	0
T1	230953	47	0	0
T2	0	44	0	0
T3	0	11	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T7	708	0	0	0
T10	0	7	0	0
T11	0	47	0	0
T12	0	73	0	0
T13	0	131	0	0
T14	0	19	0	0
T15	0	64	0	0
T16	0	37	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T22	1528	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157546850	14566	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	14566	0	0
T1	230953	59	0	0
T2	0	44	0	0
T3	0	15	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T7	708	0	0	0
T10	0	10	0	0
T11	0	57	0	0
T12	0	106	0	0
T13	0	131	0	0
T14	0	26	0	0
T15	0	89	0	0
T16	0	52	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T22	1528	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157546850	21481	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	21481	0	0
T1	230953	78	0	0
T2	0	52	0	0
T3	0	22	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T7	708	0	0	0
T10	0	12	0	0
T11	0	75	0	0
T12	0	170	0	0
T13	0	132	0	0
T14	0	35	0	0
T15	0	144	0	0
T16	0	81	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T22	1528	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157546850	10771	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	10771	0	0
T1	230953	47	0	0
T2	0	44	0	0
T3	0	11	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T7	708	0	0	0
T10	0	7	0	0
T11	0	44	0	0
T12	0	75	0	0
T13	0	131	0	0
T14	0	19	0	0
T15	0	63	0	0
T16	0	37	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T22	1528	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157546850	14566	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	14566	0	0
T1	230953	58	0	0
T2	0	44	0	0
T3	0	14	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T7	708	0	0	0
T10	0	9	0	0
T11	0	57	0	0
T12	0	104	0	0
T13	0	131	0	0
T14	0	25	0	0
T15	0	90	0	0
T16	0	60	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T22	1528	0	0	0