Module : prim_clock_div
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_clock_div_0/prim_clock_div.sv
Module self-instances :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| tb.dut.u_no_scan_io_div2_div | |||||||
| tb.dut.u_no_scan_io_div4_div |
Module Instance : tb.dut.u_no_scan_io_div2_div
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 98.63 | 100.00 | 93.15 | 100.00 | 100.00 | 100.00 | dut |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_no_scan_io_div4_div
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 98.63 | 100.00 | 93.15 | 100.00 | 100.00 | 100.00 | dut |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |