Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	157546850	155015961	0	0
AllClkBypReqTrue_A	157546850	149207	0	0
IoClkBypReqFalse_A	157546850	154930824	0	2415
IoClkBypReqTrue_A	157546850	229674	0	0
LcClkBypAckFalse_A	157546850	155031033	0	0
LcClkBypAckTrue_A	157546850	134135	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	155015961	0	0
T1	230953	230694	0	0
T4	14136	14095	0	0
T5	30045	29987	0	0
T6	5428	2364	0	0
T7	708	701	0	0
T17	1622	1302	0	0
T18	2226	1693	0	0
T19	2505	2065	0	0
T20	1469	1352	0	0
T21	904	850	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	149207	0	0
T1	230953	614	0	0
T2	0	447	0	0
T3	0	1063	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T7	708	0	0	0
T12	0	477	0	0
T13	0	849	0	0
T17	1622	240	0	0
T18	2226	320	0	0
T19	2505	412	0	0
T20	1469	0	0	0
T21	904	0	0	0
T22	1528	0	0	0
T65	0	102	0	0
T66	0	117	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	154930824	0	2415
T1	230953	230613	0	3
T4	14136	14093	0	3
T5	30045	29985	0	3
T6	5428	2356	0	3
T7	708	699	0	3
T17	1622	1258	0	3
T18	2226	1709	0	3
T19	2505	1852	0	3
T20	1469	1195	0	3
T21	904	848	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	229674	0	0
T1	230953	1414	0	0
T2	0	783	0	0
T3	0	1601	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T7	708	0	0	0
T17	1622	282	0	0
T18	2226	302	0	0
T19	2505	623	0	0
T20	1469	155	0	0
T21	904	0	0	0
T22	1528	0	0	0
T64	0	420	0	0
T65	0	275	0	0
T76	0	205	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	155031033	0	0
T1	230953	230674	0	0
T4	14136	14095	0	0
T5	30045	29987	0	0
T6	5428	2364	0	0
T7	708	701	0	0
T17	1622	1345	0	0
T18	2226	1886	0	0
T19	2505	2245	0	0
T20	1469	1296	0	0
T21	904	850	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	134135	0	0
T1	230953	814	0	0
T2	0	354	0	0
T3	0	1086	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T7	708	0	0	0
T17	1622	197	0	0
T18	2226	127	0	0
T19	2505	232	0	0
T20	1469	56	0	0
T21	904	0	0	0
T22	1528	0	0	0
T64	0	113	0	0
T65	0	162	0	0
T76	0	112	0	0