Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16053	0	0
TransStop_A	2147483647	8137	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16053	0	0
T1	3944556	240	0	0
T2	0	53	0	0
T3	0	72	0	0
T4	235616	0	0	0
T5	404776	0	0	0
T7	52044	0	0	0
T11	0	25	0	0
T12	0	32	0	0
T13	0	154	0	0
T17	13812	0	0	0
T18	8908	0	0	0
T19	40100	0	0	0
T20	12236	0	0	0
T21	14472	0	0	0
T22	61160	22	0	0
T38	0	4	0	0
T63	0	41	0	0
T67	0	31	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8137	0	0
T1	3944556	128	0	0
T2	0	29	0	0
T3	0	40	0	0
T4	235616	0	0	0
T5	404776	0	0	0
T7	52044	0	0	0
T11	0	13	0	0
T12	0	16	0	0
T13	0	74	0	0
T17	13812	0	0	0
T18	8908	0	0	0
T19	40100	0	0	0
T20	12236	0	0	0
T21	14472	0	0	0
T22	61160	12	0	0
T38	0	4	0	0
T63	0	21	0	0
T67	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	631444130	4005	0	0
TransStop_A	631444130	2024	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631444130	4005	0	0
T1	986139	66	0	0
T2	0	11	0	0
T3	0	16	0	0
T4	58904	0	0	0
T5	101194	0	0	0
T7	13011	0	0	0
T11	0	5	0	0
T12	0	6	0	0
T13	0	44	0	0
T17	3453	0	0	0
T18	2227	0	0	0
T19	10025	0	0	0
T20	3059	0	0	0
T21	3618	0	0	0
T22	15290	5	0	0
T38	0	1	0	0
T63	0	10	0	0
T67	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631444130	2024	0	0
T1	986139	33	0	0
T2	0	5	0	0
T3	0	7	0	0
T4	58904	0	0	0
T5	101194	0	0	0
T7	13011	0	0	0
T11	0	2	0	0
T12	0	3	0	0
T13	0	21	0	0
T17	3453	0	0	0
T18	2227	0	0	0
T19	10025	0	0	0
T20	3059	0	0	0
T21	3618	0	0	0
T22	15290	3	0	0
T38	0	1	0	0
T63	0	5	0	0
T67	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	631444130	4009	0	0
TransStop_A	631444130	2038	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631444130	4009	0	0
T1	986139	59	0	0
T2	0	13	0	0
T3	0	16	0	0
T4	58904	0	0	0
T5	101194	0	0	0
T7	13011	0	0	0
T11	0	7	0	0
T12	0	8	0	0
T13	0	43	0	0
T17	3453	0	0	0
T18	2227	0	0	0
T19	10025	0	0	0
T20	3059	0	0	0
T21	3618	0	0	0
T22	15290	8	0	0
T38	0	1	0	0
T63	0	14	0	0
T67	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631444130	2038	0	0
T1	986139	31	0	0
T2	0	8	0	0
T3	0	10	0	0
T4	58904	0	0	0
T5	101194	0	0	0
T7	13011	0	0	0
T11	0	3	0	0
T12	0	3	0	0
T13	0	19	0	0
T17	3453	0	0	0
T18	2227	0	0	0
T19	10025	0	0	0
T20	3059	0	0	0
T21	3618	0	0	0
T22	15290	5	0	0
T38	0	1	0	0
T63	0	7	0	0
T67	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	631444130	4009	0	0
TransStop_A	631444130	2015	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631444130	4009	0	0
T1	986139	54	0	0
T2	0	16	0	0
T3	0	19	0	0
T4	58904	0	0	0
T5	101194	0	0	0
T7	13011	0	0	0
T11	0	5	0	0
T12	0	13	0	0
T13	0	34	0	0
T17	3453	0	0	0
T18	2227	0	0	0
T19	10025	0	0	0
T20	3059	0	0	0
T21	3618	0	0	0
T22	15290	4	0	0
T38	0	1	0	0
T63	0	8	0	0
T67	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631444130	2015	0	0
T1	986139	29	0	0
T2	0	9	0	0
T3	0	11	0	0
T4	58904	0	0	0
T5	101194	0	0	0
T7	13011	0	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	18	0	0
T17	3453	0	0	0
T18	2227	0	0	0
T19	10025	0	0	0
T20	3059	0	0	0
T21	3618	0	0	0
T22	15290	2	0	0
T38	0	1	0	0
T63	0	4	0	0
T67	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	631444130	4030	0	0
TransStop_A	631444130	2060	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631444130	4030	0	0
T1	986139	61	0	0
T2	0	13	0	0
T3	0	21	0	0
T4	58904	0	0	0
T5	101194	0	0	0
T7	13011	0	0	0
T11	0	8	0	0
T12	0	5	0	0
T13	0	33	0	0
T17	3453	0	0	0
T18	2227	0	0	0
T19	10025	0	0	0
T20	3059	0	0	0
T21	3618	0	0	0
T22	15290	5	0	0
T38	0	1	0	0
T63	0	9	0	0
T67	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631444130	2060	0	0
T1	986139	35	0	0
T2	0	7	0	0
T3	0	12	0	0
T4	58904	0	0	0
T5	101194	0	0	0
T7	13011	0	0	0
T11	0	4	0	0
T12	0	3	0	0
T13	0	16	0	0
T17	3453	0	0	0
T18	2227	0	0	0
T19	10025	0	0	0
T20	3059	0	0	0
T21	3618	0	0	0
T22	15290	2	0	0
T38	0	1	0	0
T63	0	5	0	0
T67	0	3	0	0