Module Definition
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Module : prim_alert_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
tb.dut.gen_alert_tx[1].u_prim_alert_sender 100.00 100.00



Module Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T6,T1,T7 Yes T6,T1,T7 INPUT
rst_ni Yes Yes T6,T1,T2 Yes T6,T1,T7 INPUT
alert_test_i Yes Yes T31,T28,T29 Yes T31,T28,T29 INPUT
alert_req_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
alert_ack_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_state_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_rx_i.ack_n Yes Yes T6,T1,T7 Yes T6,T1,T7 INPUT
alert_rx_i.ack_p Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T6,T1,T7 Yes T6,T1,T7 OUTPUT
alert_tx_o.alert_p Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T6,T1,T7 Yes T6,T1,T7 INPUT
rst_ni Yes Yes T6,T1,T2 Yes T6,T1,T7 INPUT
alert_test_i Yes Yes T28,T29,T30 Yes T28,T29,T30 INPUT
alert_req_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
alert_ack_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_state_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_rx_i.ack_n Yes Yes T6,T1,T7 Yes T6,T1,T7 INPUT
alert_rx_i.ack_p Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T6,T1,T7 Yes T6,T1,T7 OUTPUT
alert_tx_o.alert_p Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T6,T1,T7 Yes T6,T1,T7 INPUT
rst_ni Yes Yes T6,T1,T2 Yes T6,T1,T7 INPUT
alert_test_i Yes Yes T31,T28,T29 Yes T31,T28,T29 INPUT
alert_req_i Yes Yes T37,T39,T40 Yes T37,T39,T40 INPUT
alert_ack_o Yes Yes T37,T39,T40 Yes T37,T39,T40 OUTPUT
alert_state_o Yes Yes T37,T39,T40 Yes T37,T39,T40 OUTPUT
alert_rx_i.ack_n Yes Yes T6,T1,T7 Yes T6,T1,T7 INPUT
alert_rx_i.ack_p Yes Yes T31,T37,T28 Yes T31,T37,T28 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T6,T1,T7 Yes T6,T1,T7 OUTPUT
alert_tx_o.alert_p Yes Yes T31,T37,T28 Yes T31,T37,T28 OUTPUT

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