Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT6,T1,T7
10CoveredT1,T17,T18 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T17,T18
11CoveredT1,T17,T18 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T17,T18
10CoveredT6,T1,T7
11CoveredT6,T1,T7
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 742660672 742658257 0 0
selKnown1 1787586624 1787584209 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 742660672 742658257 0 0
T1 1137075 1137075 0 0
T4 70548 70545 0 0
T5 114093 114090 0 0
T6 16312 16309 0 0
T7 12120 12117 0 0
T17 4461 4458 0 0
T18 2667 2664 0 0
T19 13267 13264 0 0
T20 3647 3644 0 0
T21 4225 4222 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1787586624 1787584209 0 0
T1 2729400 2729400 0 0
T4 169638 169635 0 0
T5 274146 274143 0 0
T6 62544 62541 0 0
T7 29289 29286 0 0
T17 9942 9939 0 0
T18 6411 6408 0 0
T19 28866 28863 0 0
T20 8808 8805 0 0
T21 10419 10416 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT6,T1,T7
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT6,T1,T7
11CoveredT6,T1,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 297233686 297232881 0 0
selKnown1 595862208 595861403 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 297233686 297232881 0 0
T1 454921 454921 0 0
T4 28219 28218 0 0
T5 45637 45636 0 0
T6 6525 6524 0 0
T7 4848 4847 0 0
T17 1911 1910 0 0
T18 1092 1091 0 0
T19 5665 5664 0 0
T20 1484 1483 0 0
T21 1690 1689 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 595862208 595861403 0 0
T1 909800 909800 0 0
T4 56546 56545 0 0
T5 91382 91381 0 0
T6 20848 20847 0 0
T7 9763 9762 0 0
T17 3314 3313 0 0
T18 2137 2136 0 0
T19 9622 9621 0 0
T20 2936 2935 0 0
T21 3473 3472 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT6,T1,T7
10CoveredT1,T17,T18 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T17,T18
11CoveredT1,T17,T18 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T17,T18
10CoveredT6,T1,T7
11CoveredT6,T1,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 296810807 296810002 0 0
selKnown1 595862208 595861403 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 296810807 296810002 0 0
T1 454694 454694 0 0
T4 28219 28218 0 0
T5 45637 45636 0 0
T6 6525 6524 0 0
T7 4848 4847 0 0
T17 1597 1596 0 0
T18 1029 1028 0 0
T19 4771 4770 0 0
T20 1422 1421 0 0
T21 1690 1689 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 595862208 595861403 0 0
T1 909800 909800 0 0
T4 56546 56545 0 0
T5 91382 91381 0 0
T6 20848 20847 0 0
T7 9763 9762 0 0
T17 3314 3313 0 0
T18 2137 2136 0 0
T19 9622 9621 0 0
T20 2936 2935 0 0
T21 3473 3472 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT6,T1,T7
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT6,T1,T7
11CoveredT6,T1,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 148616179 148615374 0 0
selKnown1 595862208 595861403 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 148615374 0 0
T1 227460 227460 0 0
T4 14110 14109 0 0
T5 22819 22818 0 0
T6 3262 3261 0 0
T7 2424 2423 0 0
T17 953 952 0 0
T18 546 545 0 0
T19 2831 2830 0 0
T20 741 740 0 0
T21 845 844 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 595862208 595861403 0 0
T1 909800 909800 0 0
T4 56546 56545 0 0
T5 91382 91381 0 0
T6 20848 20847 0 0
T7 9763 9762 0 0
T17 3314 3313 0 0
T18 2137 2136 0 0
T19 9622 9621 0 0
T20 2936 2935 0 0
T21 3473 3472 0 0

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