Module Definition
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Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_io_byp_req

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_all_byp_req

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_hi_speed_sel

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_main_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_usb_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_main_secure

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_usb_peri

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 11196259 11187580 0 0
T4 678344 676614 0 0
T5 1177033 1174482 0 0
T6 235228 109294 0 0
T7 131034 129940 0 0
T17 43154 41335 0 0
T18 30814 28048 0 0
T19 119181 118050 0 0
T20 37503 34743 0 0
T21 41600 39335 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 157546850 155167503 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 157546850 155167503 0 0
T1 230953 230756 0 0
T4 14136 14096 0 0
T5 30045 29988 0 0
T6 5428 2368 0 0
T7 708 702 0 0
T17 1622 1543 0 0
T18 2226 2014 0 0
T19 2505 2478 0 0
T20 1469 1353 0 0
T21 904 851 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 157546850 155167503 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 157546850 155167503 0 0
T1 230953 230756 0 0
T4 14136 14096 0 0
T5 30045 29988 0 0
T6 5428 2368 0 0
T7 708 702 0 0
T17 1622 1543 0 0
T18 2226 2014 0 0
T19 2505 2478 0 0
T20 1469 1353 0 0
T21 904 851 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 157546850 155167503 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 157546850 155167503 0 0
T1 230953 230756 0 0
T4 14136 14096 0 0
T5 30045 29988 0 0
T6 5428 2368 0 0
T7 708 702 0 0
T17 1622 1543 0 0
T18 2226 2014 0 0
T19 2505 2478 0 0
T20 1469 1353 0 0
T21 904 851 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 148616179 148051609 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 148051609 0 0
T1 227460 227357 0 0
T4 14110 14096 0 0
T5 22819 22788 0 0
T6 3262 2271 0 0
T7 2424 2414 0 0
T17 953 943 0 0
T18 546 515 0 0
T19 2831 2824 0 0
T20 741 706 0 0
T21 845 817 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 631443680 626705023 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 626705023 0 0
T1 986139 985339 0 0
T4 58903 58734 0 0
T5 101193 100953 0 0
T6 21717 9462 0 0
T7 13010 12898 0 0
T17 3452 3283 0 0
T18 2226 2014 0 0
T19 10024 9912 0 0
T20 3059 2819 0 0
T21 3618 3406 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 303107690 300842256 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 303107690 300842256 0 0
T1 473642 473231 0 0
T4 28274 28193 0 0
T5 57213 57098 0 0
T6 10424 4541 0 0
T7 5966 5913 0 0
T17 1657 1576 0 0
T18 1069 967 0 0
T19 4812 4758 0 0
T20 1469 1353 0 0
T21 1737 1635 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 595862208 591362850 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595862208 591362850 0 0
T1 909800 908978 0 0
T4 56546 56384 0 0
T5 91382 91151 0 0
T6 20848 9083 0 0
T7 9763 9655 0 0
T17 3314 3152 0 0
T18 2137 1934 0 0
T19 9622 9515 0 0
T20 2936 2705 0 0
T21 3473 3269 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 297233686 296104427 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 297233686 296104427 0 0
T1 454921 454716 0 0
T4 28219 28192 0 0
T5 45637 45575 0 0
T6 6525 4543 0 0
T7 4848 4827 0 0
T17 1911 1890 0 0
T18 1092 1030 0 0
T19 5665 5651 0 0
T20 1484 1415 0 0
T21 1690 1635 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 148616179 148051609 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 148051609 0 0
T1 227460 227357 0 0
T4 14110 14096 0 0
T5 22819 22788 0 0
T6 3262 2271 0 0
T7 2424 2414 0 0
T17 953 943 0 0
T18 546 515 0 0
T19 2831 2824 0 0
T20 741 706 0 0
T21 845 817 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 631443680 626705023 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 626705023 0 0
T1 986139 985339 0 0
T4 58903 58734 0 0
T5 101193 100953 0 0
T6 21717 9462 0 0
T7 13010 12898 0 0
T17 3452 3283 0 0
T18 2226 2014 0 0
T19 10024 9912 0 0
T20 3059 2819 0 0
T21 3618 3406 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 148616179 148051609 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 148051609 0 0
T1 227460 227357 0 0
T4 14110 14096 0 0
T5 22819 22788 0 0
T6 3262 2271 0 0
T7 2424 2414 0 0
T17 953 943 0 0
T18 546 515 0 0
T19 2831 2824 0 0
T20 741 706 0 0
T21 845 817 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 148616179 148051609 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 148051609 0 0
T1 227460 227357 0 0
T4 14110 14096 0 0
T5 22819 22788 0 0
T6 3262 2271 0 0
T7 2424 2414 0 0
T17 953 943 0 0
T18 546 515 0 0
T19 2831 2824 0 0
T20 741 706 0 0
T21 845 817 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 297233686 296104427 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 297233686 296104427 0 0
T1 454921 454716 0 0
T4 28219 28192 0 0
T5 45637 45575 0 0
T6 6525 4543 0 0
T7 4848 4827 0 0
T17 1911 1890 0 0
T18 1092 1030 0 0
T19 5665 5651 0 0
T20 1484 1415 0 0
T21 1690 1635 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 595862208 591362850 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595862208 591362850 0 0
T1 909800 908978 0 0
T4 56546 56384 0 0
T5 91382 91151 0 0
T6 20848 9083 0 0
T7 9763 9655 0 0
T17 3314 3152 0 0
T18 2137 1934 0 0
T19 9622 9515 0 0
T20 2936 2705 0 0
T21 3473 3269 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 303107690 300842256 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 303107690 300842256 0 0
T1 473642 473231 0 0
T4 28274 28193 0 0
T5 57213 57098 0 0
T6 10424 4541 0 0
T7 5966 5913 0 0
T17 1657 1576 0 0
T18 1069 967 0 0
T19 4812 4758 0 0
T20 1469 1353 0 0
T21 1737 1635 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 631443680 626705023 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 626705023 0 0
T1 986139 985339 0 0
T4 58903 58734 0 0
T5 101193 100953 0 0
T6 21717 9462 0 0
T7 13010 12898 0 0
T17 3452 3283 0 0
T18 2226 2014 0 0
T19 10024 9912 0 0
T20 3059 2819 0 0
T21 3618 3406 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 631443680 626705023 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 626705023 0 0
T1 986139 985339 0 0
T4 58903 58734 0 0
T5 101193 100953 0 0
T6 21717 9462 0 0
T7 13010 12898 0 0
T17 3452 3283 0 0
T18 2226 2014 0 0
T19 10024 9912 0 0
T20 3059 2819 0 0
T21 3618 3406 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 631443680 626705023 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 626705023 0 0
T1 986139 985339 0 0
T4 58903 58734 0 0
T5 101193 100953 0 0
T6 21717 9462 0 0
T7 13010 12898 0 0
T17 3452 3283 0 0
T18 2226 2014 0 0
T19 10024 9912 0 0
T20 3059 2819 0 0
T21 3618 3406 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 631443680 626705023 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 626705023 0 0
T1 986139 985339 0 0
T4 58903 58734 0 0
T5 101193 100953 0 0
T6 21717 9462 0 0
T7 13010 12898 0 0
T17 3452 3283 0 0
T18 2226 2014 0 0
T19 10024 9912 0 0
T20 3059 2819 0 0
T21 3618 3406 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%