Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	157546850	21379539	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157546850	21379539	0	57
T1	230953	19526	0	0
T2	0	8009	0	0
T3	0	6339	0	0
T4	14136	681	0	1
T5	30045	0	0	0
T7	708	0	0	0
T10	0	3500	0	1
T11	0	19757	0	1
T12	0	54942	0	0
T13	0	287865	0	0
T14	0	9010	0	1
T15	0	44105	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T22	1528	0	0	0
T23	0	0	0	1
T27	0	0	0	1
T100	0	0	0	1
T101	0	0	0	1
T102	0	0	0	1
T103	0	0	0	1