Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	158547154	5186186	0	0
clk_enables_rd_A	158547154	53927	0	0
clk_hints_rd_A	158547154	48424	0	0
extclk_ctrl_rd_A	158547154	61625	0	0
extclk_ctrl_regwen_rd_A	158547154	45793	0	0
jitter_enable_rd_A	158547154	66308	0	0
jitter_regwen_rd_A	158547154	52207	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	5186186	0	0
T1	230953	113692	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T7	708	0	0	0
T13	0	59624	0	0
T15	0	89735	0	0
T16	0	72389	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T22	1528	0	0	0
T25	0	88906	0	0
T32	0	74284	0	0
T33	0	99176	0	0
T60	0	80921	0	0
T61	0	134731	0	0
T62	0	117958	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	53927	0	0
T2	57429	1	0	0
T3	49532	3	0	0
T10	7406	0	0	0
T11	126327	9	0	0
T16	0	2754	0	0
T24	0	18	0	0
T25	0	3521	0	0
T26	77572	0	0	0
T38	1397	0	0	0
T63	3873	0	0	0
T64	2540	0	0	0
T65	2092	0	0	0
T76	2439	0	0	0
T122	0	8	0	0
T123	0	1207	0	0
T124	0	4544	0	0
T125	0	3180	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	48424	0	0
T3	49532	4	0	0
T10	7406	0	0	0
T11	126327	0	0	0
T12	529026	0	0	0
T13	164666	0	0	0
T14	29906	0	0	0
T16	0	2495	0	0
T24	0	5	0	0
T25	0	3252	0	0
T35	1045	0	0	0
T65	2092	0	0	0
T66	1648	0	0	0
T67	2429	0	0	0
T122	0	4	0	0
T123	0	1124	0	0
T124	0	3844	0	0
T125	0	2860	0	0
T126	0	2	0	0
T127	0	1563	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	61625	0	0
T1	230953	0	0	0
T2	0	50	0	0
T3	0	184	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T6	5428	9	0	0
T7	708	0	0	0
T16	0	2831	0	0
T17	1622	0	0	0
T18	2226	45	0	0
T19	2505	70	0	0
T20	1469	17	0	0
T21	904	0	0	0
T49	0	36	0	0
T51	0	30	0	0
T128	0	56	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	45793	0	0
T1	230953	0	0	0
T4	14136	0	0	0
T5	30045	0	0	0
T6	5428	6	0	0
T7	708	0	0	0
T16	0	2540	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T25	0	3019	0	0
T51	0	8	0	0
T123	0	1097	0	0
T124	0	3588	0	0
T125	0	2765	0	0
T129	0	61	0	0
T130	0	27	0	0
T131	0	29	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	66308	0	0
T2	57429	74	0	0
T3	49532	146	0	0
T10	7406	0	0	0
T11	126327	119	0	0
T16	0	2669	0	0
T24	0	296	0	0
T25	0	5162	0	0
T26	77572	0	0	0
T38	1397	0	0	0
T63	3873	0	0	0
T64	2540	0	0	0
T65	2092	0	0	0
T76	2439	0	0	0
T122	0	88	0	0
T123	0	1428	0	0
T124	0	4620	0	0
T132	0	119	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	52207	0	0
T16	244110	2792	0	0
T23	19034	0	0	0
T25	0	3822	0	0
T37	13679	0	0	0
T43	49417	0	0	0
T44	1696	0	0	0
T45	1595	0	0	0
T46	47026	0	0	0
T47	223473	0	0	0
T48	1464	0	0	0
T49	1408	0	0	0
T123	0	1272	0	0
T124	0	4007	0	0
T125	0	3391	0	0
T127	0	1792	0	0
T133	0	792	0	0
T134	0	3412	0	0
T135	0	1767	0	0
T136	0	4366	0	0