Assert Coverage for Module :
clkmgr_pwrmgr_sva_if
Assertion Details
IoStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157546850 |
125 |
0 |
0 |
T2 |
57429 |
0 |
0 |
0 |
T4 |
14136 |
0 |
0 |
0 |
T5 |
30045 |
0 |
0 |
0 |
T7 |
708 |
2 |
0 |
0 |
T17 |
1622 |
0 |
0 |
0 |
T18 |
2226 |
0 |
0 |
0 |
T19 |
2505 |
0 |
0 |
0 |
T20 |
1469 |
0 |
0 |
0 |
T21 |
904 |
0 |
0 |
0 |
T22 |
1528 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T137 |
0 |
1 |
0 |
0 |
T138 |
0 |
2 |
0 |
0 |
T139 |
0 |
4 |
0 |
0 |
T140 |
0 |
2 |
0 |
0 |
T141 |
0 |
2 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T143 |
0 |
2 |
0 |
0 |
IoStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157546850 |
125 |
0 |
0 |
T2 |
57429 |
0 |
0 |
0 |
T4 |
14136 |
0 |
0 |
0 |
T5 |
30045 |
0 |
0 |
0 |
T7 |
708 |
2 |
0 |
0 |
T17 |
1622 |
0 |
0 |
0 |
T18 |
2226 |
0 |
0 |
0 |
T19 |
2505 |
0 |
0 |
0 |
T20 |
1469 |
0 |
0 |
0 |
T21 |
904 |
0 |
0 |
0 |
T22 |
1528 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T137 |
0 |
1 |
0 |
0 |
T138 |
0 |
2 |
0 |
0 |
T139 |
0 |
4 |
0 |
0 |
T140 |
0 |
2 |
0 |
0 |
T141 |
0 |
2 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T143 |
0 |
2 |
0 |
0 |
MainStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157546850 |
144 |
0 |
0 |
T2 |
57429 |
0 |
0 |
0 |
T4 |
14136 |
0 |
0 |
0 |
T5 |
30045 |
0 |
0 |
0 |
T7 |
708 |
3 |
0 |
0 |
T17 |
1622 |
0 |
0 |
0 |
T18 |
2226 |
0 |
0 |
0 |
T19 |
2505 |
0 |
0 |
0 |
T20 |
1469 |
0 |
0 |
0 |
T21 |
904 |
0 |
0 |
0 |
T22 |
1528 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T36 |
0 |
5 |
0 |
0 |
T137 |
0 |
1 |
0 |
0 |
T138 |
0 |
2 |
0 |
0 |
T139 |
0 |
6 |
0 |
0 |
T140 |
0 |
1 |
0 |
0 |
T141 |
0 |
3 |
0 |
0 |
T142 |
0 |
3 |
0 |
0 |
T143 |
0 |
2 |
0 |
0 |
MainStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157546850 |
144 |
0 |
0 |
T2 |
57429 |
0 |
0 |
0 |
T4 |
14136 |
0 |
0 |
0 |
T5 |
30045 |
0 |
0 |
0 |
T7 |
708 |
3 |
0 |
0 |
T17 |
1622 |
0 |
0 |
0 |
T18 |
2226 |
0 |
0 |
0 |
T19 |
2505 |
0 |
0 |
0 |
T20 |
1469 |
0 |
0 |
0 |
T21 |
904 |
0 |
0 |
0 |
T22 |
1528 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T36 |
0 |
5 |
0 |
0 |
T137 |
0 |
1 |
0 |
0 |
T138 |
0 |
2 |
0 |
0 |
T139 |
0 |
6 |
0 |
0 |
T140 |
0 |
1 |
0 |
0 |
T141 |
0 |
3 |
0 |
0 |
T142 |
0 |
3 |
0 |
0 |
T143 |
0 |
2 |
0 |
0 |
UsbStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157546850 |
138 |
0 |
0 |
T2 |
57429 |
0 |
0 |
0 |
T4 |
14136 |
0 |
0 |
0 |
T5 |
30045 |
0 |
0 |
0 |
T7 |
708 |
3 |
0 |
0 |
T17 |
1622 |
0 |
0 |
0 |
T18 |
2226 |
0 |
0 |
0 |
T19 |
2505 |
0 |
0 |
0 |
T20 |
1469 |
0 |
0 |
0 |
T21 |
904 |
0 |
0 |
0 |
T22 |
1528 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T137 |
0 |
1 |
0 |
0 |
T138 |
0 |
2 |
0 |
0 |
T139 |
0 |
4 |
0 |
0 |
T140 |
0 |
2 |
0 |
0 |
T141 |
0 |
3 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T143 |
0 |
1 |
0 |
0 |
UsbStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157546850 |
138 |
0 |
0 |
T2 |
57429 |
0 |
0 |
0 |
T4 |
14136 |
0 |
0 |
0 |
T5 |
30045 |
0 |
0 |
0 |
T7 |
708 |
3 |
0 |
0 |
T17 |
1622 |
0 |
0 |
0 |
T18 |
2226 |
0 |
0 |
0 |
T19 |
2505 |
0 |
0 |
0 |
T20 |
1469 |
0 |
0 |
0 |
T21 |
904 |
0 |
0 |
0 |
T22 |
1528 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T137 |
0 |
1 |
0 |
0 |
T138 |
0 |
2 |
0 |
0 |
T139 |
0 |
4 |
0 |
0 |
T140 |
0 |
2 |
0 |
0 |
T141 |
0 |
3 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T143 |
0 |
1 |
0 |
0 |