Module Definition
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Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Module : clkmgr_cg_en_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT6,T1,T7
11CoveredT6,T1,T7

Assert Coverage for Module : clkmgr_cg_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 2147483647 50365 0 0
CgEnOn_A 2147483647 41033 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 50365 0 0
T1 6010379 150 0 0
T2 3280122 11 0 0
T4 607662 3 0 0
T5 1029685 3 0 0
T6 41059 12 0 0
T7 122944 22 0 0
T17 36631 3 0 0
T18 23067 3 0 0
T19 106854 3 0 0
T20 31627 3 0 0
T21 37151 33 0 0
T22 124631 5 0 0
T35 0 20 0 0
T36 0 20 0 0
T61 0 5 0 0
T62 0 5 0 0
T137 0 5 0 0
T138 0 10 0 0
T139 0 20 0 0
T140 0 10 0 0
T141 0 10 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 41033 0 0
T1 6010379 132 0 0
T2 3280122 27 0 0
T3 0 81 0 0
T4 607662 0 0 0
T5 1029685 0 0 0
T7 122944 19 0 0
T11 0 8 0 0
T12 0 191 0 0
T13 0 157 0 0
T17 36631 0 0 0
T18 23067 0 0 0
T19 106854 0 0 0
T20 31627 0 0 0
T21 37151 30 0 0
T22 157575 5 0 0
T35 0 32 0 0
T36 0 20 0 0
T38 0 4 0 0
T61 0 5 0 0
T62 0 4 0 0
T63 0 10 0 0
T137 0 5 0 0
T138 0 10 0 0
T139 0 20 0 0
T140 0 10 0 0
T141 0 10 0 0
T142 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 297233686 136 0 0
CgEnOn_A 297233686 136 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 297233686 136 0 0
T2 371026 0 0 0
T4 28219 0 0 0
T5 45637 0 0 0
T7 4848 2 0 0
T17 1911 0 0 0
T18 1092 0 0 0
T19 5665 0 0 0
T20 1484 0 0 0
T21 1690 0 0 0
T22 7285 0 0 0
T35 0 4 0 0
T36 0 4 0 0
T61 0 1 0 0
T62 0 1 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 4 0 0
T140 0 2 0 0
T141 0 2 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 297233686 136 0 0
T2 371026 0 0 0
T4 28219 0 0 0
T5 45637 0 0 0
T7 4848 2 0 0
T17 1911 0 0 0
T18 1092 0 0 0
T19 5665 0 0 0
T20 1484 0 0 0
T21 1690 0 0 0
T22 7285 0 0 0
T35 0 4 0 0
T36 0 4 0 0
T61 0 1 0 0
T62 0 1 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 4 0 0
T140 0 2 0 0
T141 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 148616179 136 0 0
CgEnOn_A 148616179 136 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 136 0 0
T2 185511 0 0 0
T4 14110 0 0 0
T5 22819 0 0 0
T7 2424 2 0 0
T17 953 0 0 0
T18 546 0 0 0
T19 2831 0 0 0
T20 741 0 0 0
T21 845 0 0 0
T22 3643 0 0 0
T35 0 4 0 0
T36 0 4 0 0
T61 0 1 0 0
T62 0 1 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 4 0 0
T140 0 2 0 0
T141 0 2 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 136 0 0
T2 185511 0 0 0
T4 14110 0 0 0
T5 22819 0 0 0
T7 2424 2 0 0
T17 953 0 0 0
T18 546 0 0 0
T19 2831 0 0 0
T20 741 0 0 0
T21 845 0 0 0
T22 3643 0 0 0
T35 0 4 0 0
T36 0 4 0 0
T61 0 1 0 0
T62 0 1 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 4 0 0
T140 0 2 0 0
T141 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 595862208 136 0 0
CgEnOn_A 595862208 129 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595862208 136 0 0
T2 735735 0 0 0
T4 56546 0 0 0
T5 91382 0 0 0
T7 9763 2 0 0
T17 3314 0 0 0
T18 2137 0 0 0
T19 9622 0 0 0
T20 2936 0 0 0
T21 3473 0 0 0
T22 14677 0 0 0
T35 0 4 0 0
T36 0 4 0 0
T61 0 1 0 0
T62 0 1 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 4 0 0
T140 0 2 0 0
T141 0 2 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595862208 129 0 0
T2 735735 0 0 0
T4 56546 0 0 0
T5 91382 0 0 0
T7 9763 2 0 0
T17 3314 0 0 0
T18 2137 0 0 0
T19 9622 0 0 0
T20 2936 0 0 0
T21 3473 0 0 0
T22 14677 0 0 0
T35 0 4 0 0
T36 0 4 0 0
T61 0 1 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 4 0 0
T140 0 2 0 0
T141 0 2 0 0
T142 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 631443680 147 0 0
CgEnOn_A 631443680 145 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 147 0 0
T2 808414 0 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 0 0 0
T35 0 4 0 0
T36 0 5 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 6 0 0
T140 0 1 0 0
T141 0 3 0 0
T142 0 3 0 0
T143 0 2 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 145 0 0
T2 808414 0 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 0 0 0
T35 0 4 0 0
T36 0 5 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 6 0 0
T140 0 1 0 0
T141 0 3 0 0
T142 0 3 0 0
T143 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 148616179 136 0 0
CgEnOn_A 148616179 136 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 136 0 0
T2 185511 0 0 0
T4 14110 0 0 0
T5 22819 0 0 0
T7 2424 2 0 0
T17 953 0 0 0
T18 546 0 0 0
T19 2831 0 0 0
T20 741 0 0 0
T21 845 0 0 0
T22 3643 0 0 0
T35 0 4 0 0
T36 0 4 0 0
T61 0 1 0 0
T62 0 1 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 4 0 0
T140 0 2 0 0
T141 0 2 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 136 0 0
T2 185511 0 0 0
T4 14110 0 0 0
T5 22819 0 0 0
T7 2424 2 0 0
T17 953 0 0 0
T18 546 0 0 0
T19 2831 0 0 0
T20 741 0 0 0
T21 845 0 0 0
T22 3643 0 0 0
T35 0 4 0 0
T36 0 4 0 0
T61 0 1 0 0
T62 0 1 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 4 0 0
T140 0 2 0 0
T141 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 631443680 147 0 0
CgEnOn_A 631443680 145 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 147 0 0
T2 808414 0 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 0 0 0
T35 0 4 0 0
T36 0 5 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 6 0 0
T140 0 1 0 0
T141 0 3 0 0
T142 0 3 0 0
T143 0 2 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 145 0 0
T2 808414 0 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 0 0 0
T35 0 4 0 0
T36 0 5 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 6 0 0
T140 0 1 0 0
T141 0 3 0 0
T142 0 3 0 0
T143 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 148616179 136 0 0
CgEnOn_A 148616179 136 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 136 0 0
T2 185511 0 0 0
T4 14110 0 0 0
T5 22819 0 0 0
T7 2424 2 0 0
T17 953 0 0 0
T18 546 0 0 0
T19 2831 0 0 0
T20 741 0 0 0
T21 845 0 0 0
T22 3643 0 0 0
T35 0 4 0 0
T36 0 4 0 0
T61 0 1 0 0
T62 0 1 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 4 0 0
T140 0 2 0 0
T141 0 2 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 136 0 0
T2 185511 0 0 0
T4 14110 0 0 0
T5 22819 0 0 0
T7 2424 2 0 0
T17 953 0 0 0
T18 546 0 0 0
T19 2831 0 0 0
T20 741 0 0 0
T21 845 0 0 0
T22 3643 0 0 0
T35 0 4 0 0
T36 0 4 0 0
T61 0 1 0 0
T62 0 1 0 0
T137 0 1 0 0
T138 0 2 0 0
T139 0 4 0 0
T140 0 2 0 0
T141 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT7,T35,T36
10CoveredT6,T1,T7
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 297233686 8180 0 0
CgEnOn_A 297233686 5856 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 297233686 8180 0 0
T1 454921 27 0 0
T4 28219 1 0 0
T5 45637 1 0 0
T6 6525 4 0 0
T7 4848 3 0 0
T17 1911 1 0 0
T18 1092 1 0 0
T19 5665 1 0 0
T20 1484 1 0 0
T21 1690 11 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 297233686 5856 0 0
T1 454921 21 0 0
T2 0 5 0 0
T3 0 21 0 0
T4 28219 0 0 0
T5 45637 0 0 0
T7 4848 2 0 0
T11 0 1 0 0
T12 0 60 0 0
T13 0 52 0 0
T17 1911 0 0 0
T18 1092 0 0 0
T19 5665 0 0 0
T20 1484 0 0 0
T21 1690 10 0 0
T22 7285 0 0 0
T35 0 4 0 0
T38 0 1 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT7,T35,T36
10CoveredT6,T1,T7
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 148616179 8141 0 0
CgEnOn_A 148616179 5817 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 8141 0 0
T1 227460 28 0 0
T4 14110 1 0 0
T5 22819 1 0 0
T6 3262 4 0 0
T7 2424 3 0 0
T17 953 1 0 0
T18 546 1 0 0
T19 2831 1 0 0
T20 741 1 0 0
T21 845 11 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148616179 5817 0 0
T1 227460 22 0 0
T2 0 6 0 0
T3 0 23 0 0
T4 14110 0 0 0
T5 22819 0 0 0
T7 2424 2 0 0
T11 0 1 0 0
T12 0 67 0 0
T13 0 53 0 0
T17 953 0 0 0
T18 546 0 0 0
T19 2831 0 0 0
T20 741 0 0 0
T21 845 10 0 0
T22 3643 0 0 0
T35 0 4 0 0
T38 0 1 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT7,T35,T36
10CoveredT6,T1,T7
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 595862208 8235 0 0
CgEnOn_A 595862208 5904 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595862208 8235 0 0
T1 909800 29 0 0
T4 56546 1 0 0
T5 91382 1 0 0
T6 20848 4 0 0
T7 9763 3 0 0
T17 3314 1 0 0
T18 2137 1 0 0
T19 9622 1 0 0
T20 2936 1 0 0
T21 3473 11 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595862208 5904 0 0
T1 909800 23 0 0
T2 0 5 0 0
T3 0 21 0 0
T4 56546 0 0 0
T5 91382 0 0 0
T7 9763 2 0 0
T11 0 1 0 0
T12 0 58 0 0
T13 0 52 0 0
T17 3314 0 0 0
T18 2137 0 0 0
T19 9622 0 0 0
T20 2936 0 0 0
T21 3473 10 0 0
T22 14677 0 0 0
T35 0 4 0 0
T38 0 1 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT7,T35,T36
10CoveredT6,T1,T7
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 303107690 8194 0 0
CgEnOn_A 303107690 5860 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 303107690 8194 0 0
T1 473642 27 0 0
T4 28274 1 0 0
T5 57213 1 0 0
T6 10424 4 0 0
T7 5966 4 0 0
T17 1657 1 0 0
T18 1069 1 0 0
T19 4812 1 0 0
T20 1469 1 0 0
T21 1737 11 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 303107690 5860 0 0
T1 473642 21 0 0
T2 0 5 0 0
T3 0 24 0 0
T4 28274 0 0 0
T5 57213 0 0 0
T7 5966 3 0 0
T11 0 1 0 0
T12 0 61 0 0
T13 0 54 0 0
T17 1657 0 0 0
T18 1069 0 0 0
T19 4812 0 0 0
T20 1469 0 0 0
T21 1737 10 0 0
T22 7339 0 0 0
T35 0 4 0 0
T38 0 1 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T22,T2
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 631443680 4152 0 0
CgEnOn_A 631443680 4150 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 4152 0 0
T1 986139 66 0 0
T2 0 11 0 0
T3 0 16 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T11 0 5 0 0
T12 0 6 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 5 0 0
T38 0 1 0 0
T63 0 10 0 0
T67 0 7 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 4150 0 0
T1 986139 66 0 0
T2 0 11 0 0
T3 0 16 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T11 0 5 0 0
T12 0 6 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 5 0 0
T38 0 1 0 0
T63 0 10 0 0
T67 0 7 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T22,T2
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 631443680 4156 0 0
CgEnOn_A 631443680 4154 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 4156 0 0
T1 986139 59 0 0
T2 0 13 0 0
T3 0 16 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T11 0 7 0 0
T12 0 8 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 8 0 0
T38 0 1 0 0
T63 0 14 0 0
T67 0 8 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 4154 0 0
T1 986139 59 0 0
T2 0 13 0 0
T3 0 16 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T11 0 7 0 0
T12 0 8 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 8 0 0
T38 0 1 0 0
T63 0 14 0 0
T67 0 8 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T22,T2
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 631443680 4156 0 0
CgEnOn_A 631443680 4154 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 4156 0 0
T1 986139 54 0 0
T2 0 16 0 0
T3 0 19 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T11 0 5 0 0
T12 0 13 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 4 0 0
T38 0 1 0 0
T63 0 8 0 0
T67 0 11 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 4154 0 0
T1 986139 54 0 0
T2 0 16 0 0
T3 0 19 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T11 0 5 0 0
T12 0 13 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 4 0 0
T38 0 1 0 0
T63 0 8 0 0
T67 0 11 0 0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS2411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1


Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T22,T2
11CoveredT6,T1,T7

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CgEnOff_A 631443680 4177 0 0
CgEnOn_A 631443680 4175 0 0


CgEnOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 4177 0 0
T1 986139 61 0 0
T2 0 13 0 0
T3 0 21 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T11 0 8 0 0
T12 0 5 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 5 0 0
T38 0 1 0 0
T63 0 9 0 0
T67 0 5 0 0

CgEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 631443680 4175 0 0
T1 986139 61 0 0
T2 0 13 0 0
T3 0 21 0 0
T4 58903 0 0 0
T5 101193 0 0 0
T7 13010 3 0 0
T11 0 8 0 0
T12 0 5 0 0
T17 3452 0 0 0
T18 2226 0 0 0
T19 10024 0 0 0
T20 3059 0 0 0
T21 3618 0 0 0
T22 15290 5 0 0
T38 0 1 0 0
T63 0 9 0 0
T67 0 5 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%