Line Coverage for Module :
clkmgr_gated_clock_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 18 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
Cond Coverage for Module :
clkmgr_gated_clock_sva_if
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 18
EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
------------1----------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T21 |
0 | 1 | Covered | T1,T21,T2 |
1 | 0 | Covered | T6,T1,T7 |
LINE 18
SUB-EXPRESSION (sw_clk_en && ip_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T21,T2 |
1 | 0 | Covered | T7,T35,T36 |
1 | 1 | Covered | T6,T1,T7 |
Assert Coverage for Module :
clkmgr_gated_clock_sva_if
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
GateClose_A |
1344821379 |
15032 |
0 |
0 |
GateOpen_A |
1344821379 |
15032 |
0 |
0 |
GateClose_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1344821379 |
15032 |
0 |
0 |
T1 |
2065823 |
54 |
0 |
0 |
T2 |
0 |
12 |
0 |
0 |
T3 |
0 |
53 |
0 |
0 |
T4 |
127150 |
0 |
0 |
0 |
T5 |
217054 |
0 |
0 |
0 |
T7 |
23004 |
9 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
164 |
0 |
0 |
T13 |
0 |
136 |
0 |
0 |
T17 |
7837 |
0 |
0 |
0 |
T18 |
4845 |
0 |
0 |
0 |
T19 |
22933 |
0 |
0 |
0 |
T20 |
6632 |
0 |
0 |
0 |
T21 |
7746 |
25 |
0 |
0 |
T22 |
32946 |
0 |
0 |
0 |
T35 |
0 |
16 |
0 |
0 |
T38 |
0 |
4 |
0 |
0 |
GateOpen_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1344821379 |
15032 |
0 |
0 |
T1 |
2065823 |
54 |
0 |
0 |
T2 |
0 |
12 |
0 |
0 |
T3 |
0 |
53 |
0 |
0 |
T4 |
127150 |
0 |
0 |
0 |
T5 |
217054 |
0 |
0 |
0 |
T7 |
23004 |
9 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
164 |
0 |
0 |
T13 |
0 |
136 |
0 |
0 |
T17 |
7837 |
0 |
0 |
0 |
T18 |
4845 |
0 |
0 |
0 |
T19 |
22933 |
0 |
0 |
0 |
T20 |
6632 |
0 |
0 |
0 |
T21 |
7746 |
25 |
0 |
0 |
T22 |
32946 |
0 |
0 |
0 |
T35 |
0 |
16 |
0 |
0 |
T38 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 18 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 18
EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
------------1----------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T21 |
0 | 1 | Covered | T1,T21,T2 |
1 | 0 | Covered | T6,T1,T7 |
LINE 18
SUB-EXPRESSION (sw_clk_en && ip_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T21,T2 |
1 | 0 | Covered | T7,T35,T36 |
1 | 1 | Covered | T6,T1,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
GateClose_A |
148616588 |
3694 |
0 |
0 |
GateOpen_A |
148616588 |
3694 |
0 |
0 |
GateClose_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
148616588 |
3694 |
0 |
0 |
T1 |
227460 |
13 |
0 |
0 |
T2 |
0 |
3 |
0 |
0 |
T3 |
0 |
14 |
0 |
0 |
T4 |
14110 |
0 |
0 |
0 |
T5 |
22819 |
0 |
0 |
0 |
T7 |
2425 |
2 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
42 |
0 |
0 |
T13 |
0 |
34 |
0 |
0 |
T17 |
953 |
0 |
0 |
0 |
T18 |
546 |
0 |
0 |
0 |
T19 |
2832 |
0 |
0 |
0 |
T20 |
742 |
0 |
0 |
0 |
T21 |
845 |
6 |
0 |
0 |
T22 |
3643 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
GateOpen_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
148616588 |
3694 |
0 |
0 |
T1 |
227460 |
13 |
0 |
0 |
T2 |
0 |
3 |
0 |
0 |
T3 |
0 |
14 |
0 |
0 |
T4 |
14110 |
0 |
0 |
0 |
T5 |
22819 |
0 |
0 |
0 |
T7 |
2425 |
2 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
42 |
0 |
0 |
T13 |
0 |
34 |
0 |
0 |
T17 |
953 |
0 |
0 |
0 |
T18 |
546 |
0 |
0 |
0 |
T19 |
2832 |
0 |
0 |
0 |
T20 |
742 |
0 |
0 |
0 |
T21 |
845 |
6 |
0 |
0 |
T22 |
3643 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 18 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 18
EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
------------1----------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T21 |
0 | 1 | Covered | T1,T21,T2 |
1 | 0 | Covered | T6,T1,T7 |
LINE 18
SUB-EXPRESSION (sw_clk_en && ip_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T21,T2 |
1 | 0 | Covered | T7,T35,T36 |
1 | 1 | Covered | T6,T1,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
GateClose_A |
297234065 |
3750 |
0 |
0 |
GateOpen_A |
297234065 |
3750 |
0 |
0 |
GateClose_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
297234065 |
3750 |
0 |
0 |
T1 |
454921 |
14 |
0 |
0 |
T2 |
0 |
3 |
0 |
0 |
T3 |
0 |
12 |
0 |
0 |
T4 |
28220 |
0 |
0 |
0 |
T5 |
45638 |
0 |
0 |
0 |
T7 |
4849 |
2 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
40 |
0 |
0 |
T13 |
0 |
34 |
0 |
0 |
T17 |
1911 |
0 |
0 |
0 |
T18 |
1092 |
0 |
0 |
0 |
T19 |
5666 |
0 |
0 |
0 |
T20 |
1484 |
0 |
0 |
0 |
T21 |
1690 |
5 |
0 |
0 |
T22 |
7286 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
GateOpen_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
297234065 |
3750 |
0 |
0 |
T1 |
454921 |
14 |
0 |
0 |
T2 |
0 |
3 |
0 |
0 |
T3 |
0 |
12 |
0 |
0 |
T4 |
28220 |
0 |
0 |
0 |
T5 |
45638 |
0 |
0 |
0 |
T7 |
4849 |
2 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
40 |
0 |
0 |
T13 |
0 |
34 |
0 |
0 |
T17 |
1911 |
0 |
0 |
0 |
T18 |
1092 |
0 |
0 |
0 |
T19 |
5666 |
0 |
0 |
0 |
T20 |
1484 |
0 |
0 |
0 |
T21 |
1690 |
5 |
0 |
0 |
T22 |
7286 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 18 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 18
EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
------------1----------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T21 |
0 | 1 | Covered | T1,T21,T2 |
1 | 0 | Covered | T6,T1,T7 |
LINE 18
SUB-EXPRESSION (sw_clk_en && ip_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T21,T2 |
1 | 0 | Covered | T7,T35,T36 |
1 | 1 | Covered | T6,T1,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
GateClose_A |
595862631 |
3803 |
0 |
0 |
GateOpen_A |
595862631 |
3803 |
0 |
0 |
GateClose_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595862631 |
3803 |
0 |
0 |
T1 |
909800 |
15 |
0 |
0 |
T2 |
0 |
3 |
0 |
0 |
T3 |
0 |
14 |
0 |
0 |
T4 |
56546 |
0 |
0 |
0 |
T5 |
91383 |
0 |
0 |
0 |
T7 |
9763 |
2 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
40 |
0 |
0 |
T13 |
0 |
34 |
0 |
0 |
T17 |
3315 |
0 |
0 |
0 |
T18 |
2138 |
0 |
0 |
0 |
T19 |
9623 |
0 |
0 |
0 |
T20 |
2937 |
0 |
0 |
0 |
T21 |
3474 |
7 |
0 |
0 |
T22 |
14678 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
GateOpen_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
595862631 |
3803 |
0 |
0 |
T1 |
909800 |
15 |
0 |
0 |
T2 |
0 |
3 |
0 |
0 |
T3 |
0 |
14 |
0 |
0 |
T4 |
56546 |
0 |
0 |
0 |
T5 |
91383 |
0 |
0 |
0 |
T7 |
9763 |
2 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
40 |
0 |
0 |
T13 |
0 |
34 |
0 |
0 |
T17 |
3315 |
0 |
0 |
0 |
T18 |
2138 |
0 |
0 |
0 |
T19 |
9623 |
0 |
0 |
0 |
T20 |
2937 |
0 |
0 |
0 |
T21 |
3474 |
7 |
0 |
0 |
T22 |
14678 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 18 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 18
EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
------------1----------- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T21 |
0 | 1 | Covered | T1,T21,T2 |
1 | 0 | Covered | T6,T1,T7 |
LINE 18
SUB-EXPRESSION (sw_clk_en && ip_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T21,T2 |
1 | 0 | Covered | T7,T35,T36 |
1 | 1 | Covered | T6,T1,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
GateClose_A |
303108095 |
3785 |
0 |
0 |
GateOpen_A |
303108095 |
3785 |
0 |
0 |
GateClose_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
303108095 |
3785 |
0 |
0 |
T1 |
473642 |
12 |
0 |
0 |
T2 |
0 |
3 |
0 |
0 |
T3 |
0 |
13 |
0 |
0 |
T4 |
28274 |
0 |
0 |
0 |
T5 |
57214 |
0 |
0 |
0 |
T7 |
5967 |
3 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
42 |
0 |
0 |
T13 |
0 |
34 |
0 |
0 |
T17 |
1658 |
0 |
0 |
0 |
T18 |
1069 |
0 |
0 |
0 |
T19 |
4812 |
0 |
0 |
0 |
T20 |
1469 |
0 |
0 |
0 |
T21 |
1737 |
7 |
0 |
0 |
T22 |
7339 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
GateOpen_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
303108095 |
3785 |
0 |
0 |
T1 |
473642 |
12 |
0 |
0 |
T2 |
0 |
3 |
0 |
0 |
T3 |
0 |
13 |
0 |
0 |
T4 |
28274 |
0 |
0 |
0 |
T5 |
57214 |
0 |
0 |
0 |
T7 |
5967 |
3 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
42 |
0 |
0 |
T13 |
0 |
34 |
0 |
0 |
T17 |
1658 |
0 |
0 |
0 |
T18 |
1069 |
0 |
0 |
0 |
T19 |
4812 |
0 |
0 |
0 |
T20 |
1469 |
0 |
0 |
0 |
T21 |
1737 |
7 |
0 |
0 |
T22 |
7339 |
0 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |