Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 620830 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 3572050 1 T5 31 T6 6 T23 12



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1029182 1 T5 42 T6 7 T23 12
values[0x0] 1454662 1 T5 21 T6 5 T23 14
values[0x1] 1709036 1 T5 18 T6 10 T23 11



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 343211 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 3849669 1 T5 41 T6 10 T23 14



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 16739 1 T5 2 T6 3 T2 394
valid_sources[0x01] 15802 1 T5 1 T23 1 T1 1
valid_sources[0x02] 15570 1 T1 1 T2 406 T20 5
valid_sources[0x03] 17113 1 T2 396 T20 7 T3 1
valid_sources[0x04] 16036 1 T26 3 T1 2 T2 384
valid_sources[0x05] 16824 1 T23 2 T24 1 T2 362
valid_sources[0x06] 15882 1 T2 353 T20 1 T3 4
valid_sources[0x07] 15857 1 T5 1 T6 1 T2 335
valid_sources[0x08] 17050 1 T24 1 T1 1 T2 390
valid_sources[0x09] 16591 1 T5 1 T1 5 T2 377
valid_sources[0x0a] 15903 1 T1 1 T2 356 T20 1
valid_sources[0x0b] 15458 1 T23 1 T2 363 T20 1
valid_sources[0x0c] 15678 1 T24 1 T1 3 T2 384
valid_sources[0x0d] 20368 1 T2 349 T20 2 T10 3
valid_sources[0x0e] 16381 1 T5 1 T6 2 T24 2
valid_sources[0x0f] 16641 1 T2 382 T20 2 T3 5
valid_sources[0x10] 15827 1 T24 1 T2 396 T20 6
valid_sources[0x11] 16360 1 T23 1 T1 4 T2 359
valid_sources[0x12] 16455 1 T24 1 T2 345 T20 4
valid_sources[0x13] 16773 1 T1 1 T2 364 T17 5
valid_sources[0x14] 17581 1 T2 376 T10 2 T30 1
valid_sources[0x15] 16137 1 T2 368 T17 2 T10 3
valid_sources[0x16] 16378 1 T1 1 T2 344 T20 2
valid_sources[0x17] 15001 1 T24 1 T2 365 T20 4
valid_sources[0x18] 16220 1 T2 390 T20 3 T3 6
valid_sources[0x19] 15739 1 T5 1 T24 1 T2 394
valid_sources[0x1a] 16532 1 T5 1 T1 3 T2 367
valid_sources[0x1b] 16059 1 T1 3 T2 372 T17 1
valid_sources[0x1c] 16982 1 T5 1 T23 1 T1 1
valid_sources[0x1d] 16123 1 T2 383 T20 2 T30 3
valid_sources[0x1e] 15177 1 T24 3 T2 388 T20 3
valid_sources[0x1f] 15878 1 T2 377 T17 1 T20 1
valid_sources[0x20] 15860 1 T2 414 T20 8 T3 8
valid_sources[0x21] 15526 1 T23 1 T2 388 T17 1
valid_sources[0x22] 17215 1 T5 1 T1 3 T2 385
valid_sources[0x23] 15829 1 T2 384 T20 7 T30 2
valid_sources[0x24] 18324 1 T2 367 T20 3 T3 5
valid_sources[0x25] 16075 1 T5 2 T26 8 T1 1
valid_sources[0x26] 18142 1 T5 1 T1 1 T2 371
valid_sources[0x27] 16204 1 T1 2 T2 387 T20 8
valid_sources[0x28] 16998 1 T1 3 T2 346 T3 1
valid_sources[0x29] 16147 1 T2 385 T20 3 T3 6
valid_sources[0x2a] 16125 1 T23 1 T2 363 T17 1
valid_sources[0x2b] 16882 1 T1 2 T2 371 T17 1
valid_sources[0x2c] 15579 1 T24 1 T2 357 T20 1
valid_sources[0x2d] 15221 1 T2 333 T20 2 T3 2
valid_sources[0x2e] 16307 1 T1 1 T2 353 T20 1
valid_sources[0x2f] 15999 1 T2 333 T20 2 T30 4
valid_sources[0x30] 16362 1 T2 369 T20 10 T31 2
valid_sources[0x31] 16706 1 T5 1 T23 1 T24 1
valid_sources[0x32] 16871 1 T24 1 T1 4 T2 323
valid_sources[0x33] 17772 1 T1 4 T2 365 T20 7
valid_sources[0x34] 16811 1 T1 2 T2 340 T20 12
valid_sources[0x35] 15969 1 T23 1 T2 357 T20 2
valid_sources[0x36] 17038 1 T2 399 T20 1 T30 2
valid_sources[0x37] 17019 1 T2 355 T20 4 T3 1
valid_sources[0x38] 16816 1 T5 1 T1 2 T2 390
valid_sources[0x39] 16400 1 T1 1 T2 363 T20 5
valid_sources[0x3a] 17172 1 T5 2 T1 1 T2 358
valid_sources[0x3b] 15698 1 T1 2 T2 385 T17 5
valid_sources[0x3c] 16296 1 T2 361 T20 3 T3 1
valid_sources[0x3d] 16179 1 T5 1 T1 4 T2 358
valid_sources[0x3e] 17300 1 T1 2 T2 360 T17 1
valid_sources[0x3f] 15137 1 T5 1 T24 1 T1 1
valid_sources[0x40] 16153 1 T2 402 T17 1 T20 3
valid_sources[0x41] 16363 1 T2 396 T3 9 T22 5
valid_sources[0x42] 15920 1 T1 3 T2 360 T20 4
valid_sources[0x43] 15987 1 T24 1 T2 376 T30 1
valid_sources[0x44] 16056 1 T2 377 T20 3 T3 3
valid_sources[0x45] 14949 1 T6 1 T1 2 T2 354
valid_sources[0x46] 15337 1 T2 351 T20 2 T10 3
valid_sources[0x47] 15689 1 T24 1 T2 400 T20 2
valid_sources[0x48] 16471 1 T5 1 T6 1 T23 2
valid_sources[0x49] 15273 1 T2 386 T20 2 T30 1
valid_sources[0x4a] 16655 1 T1 3 T2 373 T20 4
valid_sources[0x4b] 16307 1 T1 3 T2 369 T20 4
valid_sources[0x4c] 15651 1 T2 363 T20 7 T3 7
valid_sources[0x4d] 16252 1 T5 1 T24 1 T2 393
valid_sources[0x4e] 15960 1 T5 1 T23 1 T2 366
valid_sources[0x4f] 16194 1 T1 1 T2 344 T20 2
valid_sources[0x50] 16567 1 T5 2 T6 1 T2 352
valid_sources[0x51] 16074 1 T5 1 T1 1 T2 374
valid_sources[0x52] 17003 1 T5 1 T1 1 T2 380
valid_sources[0x53] 16183 1 T2 355 T20 3 T3 2
valid_sources[0x54] 16692 1 T24 1 T2 349 T17 2
valid_sources[0x55] 16460 1 T2 345 T20 2 T30 2
valid_sources[0x56] 15064 1 T1 2 T2 376 T20 1
valid_sources[0x57] 15756 1 T5 1 T26 13 T2 379
valid_sources[0x58] 14879 1 T2 349 T17 3 T20 10
valid_sources[0x59] 14324 1 T5 1 T2 406 T20 7
valid_sources[0x5a] 17853 1 T5 1 T6 2 T23 1
valid_sources[0x5b] 15862 1 T2 376 T20 3 T3 6
valid_sources[0x5c] 16728 1 T2 382 T20 2 T30 3
valid_sources[0x5d] 15719 1 T1 3 T2 376 T17 1
valid_sources[0x5e] 18023 1 T1 1 T2 378 T20 4
valid_sources[0x5f] 15366 1 T2 343 T17 1 T20 3
valid_sources[0x60] 16215 1 T2 384 T20 4 T3 11
valid_sources[0x61] 16040 1 T24 2 T1 1 T2 391
valid_sources[0x62] 16825 1 T1 1 T2 379 T20 1
valid_sources[0x63] 14413 1 T5 1 T2 373 T20 4
valid_sources[0x64] 16604 1 T23 3 T1 2 T2 380
valid_sources[0x65] 16205 1 T23 1 T2 385 T20 3
valid_sources[0x66] 15593 1 T2 380 T20 5 T3 2
valid_sources[0x67] 15848 1 T24 1 T27 1 T2 371
valid_sources[0x68] 15360 1 T2 364 T20 2 T3 1
valid_sources[0x69] 16208 1 T1 2 T2 372 T20 3
valid_sources[0x6a] 16282 1 T1 4 T2 379 T20 1
valid_sources[0x6b] 15392 1 T2 345 T20 8 T3 2
valid_sources[0x6c] 16520 1 T5 1 T1 1 T2 366
valid_sources[0x6d] 15433 1 T2 382 T20 4 T3 9
valid_sources[0x6e] 17075 1 T5 1 T24 1 T2 353
valid_sources[0x6f] 15893 1 T24 1 T1 3 T2 375
valid_sources[0x70] 16083 1 T1 1 T2 343 T20 3
valid_sources[0x71] 14913 1 T2 362 T20 1 T3 1
valid_sources[0x72] 17064 1 T6 1 T23 1 T2 385
valid_sources[0x73] 18029 1 T2 373 T20 4 T10 2
valid_sources[0x74] 16555 1 T1 1 T2 376 T17 1
valid_sources[0x75] 14939 1 T1 4 T2 390 T20 4
valid_sources[0x76] 17151 1 T1 3 T2 363 T20 5
valid_sources[0x77] 15916 1 T2 370 T17 2 T20 3
valid_sources[0x78] 18539 1 T24 1 T1 1 T2 408
valid_sources[0x79] 14895 1 T5 1 T1 1 T2 377
valid_sources[0x7a] 15584 1 T2 375 T17 2 T20 4
valid_sources[0x7b] 16107 1 T5 1 T24 1 T1 2
valid_sources[0x7c] 15392 1 T5 1 T2 375 T20 2
valid_sources[0x7d] 17325 1 T5 1 T2 362 T20 3
valid_sources[0x7e] 15725 1 T2 381 T20 4 T3 3
valid_sources[0x7f] 16263 1 T6 1 T2 352 T20 2
valid_sources[0x80] 18751 1 T2 349 T20 1 T10 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 901437 1 T5 21 T6 3 T23 5
values[0x0] all_enables biggest_size 1359224 1 T5 5 T6 1 T23 6
values[0x1] all_enables biggest_size 1311389 1 T5 5 T6 2 T23 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%