Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
275349 |
1 |
|
|
T5 |
9 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
213988682 |
1 |
|
|
T5 |
1183 |
|
T6 |
798 |
|
T7 |
651 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8768 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
25 |
auto[1] |
214255263 |
1 |
|
|
T5 |
1190 |
|
T6 |
798 |
|
T7 |
628 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
120188346 |
1 |
|
|
T5 |
1183 |
|
T6 |
752 |
|
T7 |
653 |
auto[1] |
94075685 |
1 |
|
|
T5 |
9 |
|
T6 |
48 |
|
T23 |
218 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5252 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T23 |
2 |
auto[0] |
auto[0] |
auto[1] |
1582 |
1 |
|
|
T5 |
2 |
|
T24 |
2 |
|
T25 |
2 |
auto[0] |
auto[1] |
auto[0] |
195597 |
1 |
|
|
T5 |
7 |
|
T25 |
217 |
|
T1 |
6 |
auto[0] |
auto[1] |
auto[1] |
72918 |
1 |
|
|
T25 |
52 |
|
T2 |
1369 |
|
T3 |
12 |
auto[1] |
auto[1] |
auto[0] |
119985563 |
1 |
|
|
T5 |
1176 |
|
T6 |
750 |
|
T7 |
628 |
auto[1] |
auto[1] |
auto[1] |
94001185 |
1 |
|
|
T5 |
7 |
|
T6 |
48 |
|
T23 |
218 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
150608 |
1 |
|
|
T5 |
5 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
106979709 |
1 |
|
|
T5 |
590 |
|
T6 |
397 |
|
T7 |
324 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7811 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
13 |
auto[1] |
107122506 |
1 |
|
|
T5 |
593 |
|
T6 |
397 |
|
T7 |
313 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60092473 |
1 |
|
|
T5 |
591 |
|
T6 |
375 |
|
T7 |
326 |
auto[1] |
47037844 |
1 |
|
|
T5 |
4 |
|
T6 |
24 |
|
T23 |
108 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5252 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T23 |
2 |
auto[0] |
auto[0] |
auto[1] |
1582 |
1 |
|
|
T5 |
2 |
|
T24 |
2 |
|
T25 |
2 |
auto[0] |
auto[1] |
auto[0] |
106573 |
1 |
|
|
T5 |
3 |
|
T25 |
89 |
|
T1 |
3 |
auto[0] |
auto[1] |
auto[1] |
37201 |
1 |
|
|
T25 |
26 |
|
T2 |
748 |
|
T3 |
6 |
auto[1] |
auto[1] |
auto[0] |
59979671 |
1 |
|
|
T5 |
588 |
|
T6 |
373 |
|
T7 |
313 |
auto[1] |
auto[1] |
auto[1] |
46999061 |
1 |
|
|
T5 |
2 |
|
T6 |
24 |
|
T23 |
108 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
635177 |
1 |
|
|
T5 |
15 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
425457291 |
1 |
|
|
T5 |
2368 |
|
T6 |
1572 |
|
T7 |
1303 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10707 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
48 |
auto[1] |
426081761 |
1 |
|
|
T5 |
2381 |
|
T6 |
1572 |
|
T7 |
1257 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
237941129 |
1 |
|
|
T5 |
2366 |
|
T6 |
1478 |
|
T7 |
1305 |
auto[1] |
188151339 |
1 |
|
|
T5 |
17 |
|
T6 |
96 |
|
T23 |
434 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5252 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T23 |
2 |
auto[0] |
auto[0] |
auto[1] |
1582 |
1 |
|
|
T5 |
2 |
|
T24 |
2 |
|
T25 |
2 |
auto[0] |
auto[1] |
auto[0] |
483158 |
1 |
|
|
T5 |
13 |
|
T25 |
462 |
|
T1 |
12 |
auto[0] |
auto[1] |
auto[1] |
145185 |
1 |
|
|
T25 |
126 |
|
T2 |
2987 |
|
T3 |
25 |
auto[1] |
auto[1] |
auto[0] |
237448846 |
1 |
|
|
T5 |
2353 |
|
T6 |
1476 |
|
T7 |
1257 |
auto[1] |
auto[1] |
auto[1] |
188004572 |
1 |
|
|
T5 |
15 |
|
T6 |
96 |
|
T23 |
434 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
295185 |
1 |
|
|
T5 |
9 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
218131784 |
1 |
|
|
T5 |
1183 |
|
T6 |
786 |
|
T7 |
627 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8502 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
16 |
auto[1] |
218418467 |
1 |
|
|
T5 |
1190 |
|
T6 |
786 |
|
T7 |
613 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
122297180 |
1 |
|
|
T5 |
1183 |
|
T6 |
740 |
|
T7 |
629 |
auto[1] |
96129789 |
1 |
|
|
T5 |
9 |
|
T6 |
48 |
|
T23 |
218 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5240 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T23 |
2 |
auto[0] |
auto[0] |
auto[1] |
1594 |
1 |
|
|
T5 |
2 |
|
T24 |
2 |
|
T25 |
2 |
auto[0] |
auto[1] |
auto[0] |
214897 |
1 |
|
|
T5 |
7 |
|
T25 |
241 |
|
T1 |
6 |
auto[0] |
auto[1] |
auto[1] |
73454 |
1 |
|
|
T25 |
60 |
|
T2 |
1492 |
|
T3 |
13 |
auto[1] |
auto[1] |
auto[0] |
122075375 |
1 |
|
|
T5 |
1176 |
|
T6 |
738 |
|
T7 |
613 |
auto[1] |
auto[1] |
auto[1] |
96054741 |
1 |
|
|
T5 |
7 |
|
T6 |
48 |
|
T23 |
218 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |