Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

Group : clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
TransAes	100.00	1	100	1	64	64
TransHmac	100.00	1	100	1	64	64
TransKmac	100.00	1	100	1	64	64
TransOtbn	100.00	1	100	1	64	64

---

Group Instance : TransAes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransAes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransAes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransAes

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransHmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransHmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransHmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransHmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransKmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransKmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransKmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransKmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransOtbn

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransOtbn

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransOtbn

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransOtbn

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1451189

1

T5

234

T6

2

T7

2

auto[1]

453894103

1

T5

2248

T6

1638

T7

1273

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

402357603

1

T5

2482

T6

1465

T7

1261

auto[1]

52987689

1

T6

175

T7

14

T23

644

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10025

1

T5

2

T6

2

T7

16

auto[1]

455335267

1

T5

2480

T6

1638

T7

1259

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255092578

1

T5

2465

T6

1540

T7

1275

auto[1]

200252714

1

T5

17

T6

100

T23

451

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2354

1

T13

2

T65

2

T37

6

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T2

4

T68

2

T37

2

auto[0]

auto[1]

auto[0]

auto[0]

530081

1

T5

232

T24

657

T26

675

auto[0]

auto[1]

auto[0]

auto[1]

358883

1

T2

1382

T3

166

T111

88

auto[0]

auto[1]

auto[1]

auto[0]

466643

1

T24

988

T26

2218

T2

8994

auto[0]

auto[1]

auto[1]

auto[1]

88748

1

T24

326

T26

696

T2

2067

auto[1]

auto[1]

auto[0]

auto[0]

214787650

1

T5

2233

T6

1407

T7

1255

auto[1]

auto[1]

auto[0]

auto[1]

39407535

1

T6

131

T7

4

T23

437

auto[1]

auto[1]

auto[1]

auto[0]

186566994

1

T5

15

T6

56

T23

244

auto[1]

auto[1]

auto[1]

auto[1]

13128733

1

T6

44

T23

207

T24

1129

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1333825

1

T5

185

T6

2

T7

2

auto[1]

454011467

1

T5

2297

T6

1638

T7

1273

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

408845501

1

T5

2482

T6

1540

T7

1256

auto[1]

46499791

1

T6

100

T7

19

T23

434

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10025

1

T5

2

T6

2

T7

16

auto[1]

455335267

1

T5

2480

T6

1638

T7

1259

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255092578

1

T5

2465

T6

1540

T7

1275

auto[1]

200252714

1

T5

17

T6

100

T23

451

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2354

1

T2

2

T68

2

T37

2

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T2

2

T68

4

T37

2

auto[0]

auto[1]

auto[0]

auto[0]

466084

1

T5

183

T26

813

T1

338

auto[0]

auto[1]

auto[0]

auto[1]

347277

1

T2

1574

T3

311

T111

44

auto[0]

auto[1]

auto[1]

auto[0]

424689

1

T24

1650

T26

4166

T2

7126

auto[0]

auto[1]

auto[1]

auto[1]

88941

1

T24

978

T26

323

T2

2034

auto[1]

auto[1]

auto[0]

auto[0]

224335254

1

T5

2282

T6

1538

T7

1242

auto[1]

auto[1]

auto[0]

auto[1]

29935534

1

T7

17

T23

345

T25

7013

auto[1]

auto[1]

auto[1]

auto[0]

183613532

1

T5

15

T23

362

T24

10692

auto[1]

auto[1]

auto[1]

auto[1]

16123956

1

T6

100

T23

89

T24

1447

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1265183

1

T5

122

T6

2

T7

2

auto[1]

454080109

1

T5

2360

T6

1638

T7

1273

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

376013290

1

T5

2482

T6

1492

T7

1275

auto[1]

79332002

1

T6

148

T23

464

T24

970

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10025

1

T5

2

T6

2

T7

16

auto[1]

455335267

1

T5

2480

T6

1638

T7

1259

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255092578

1

T5

2465

T6

1540

T7

1275

auto[1]

200252714

1

T5

17

T6

100

T23

451

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2368

1

T2

2

T13

2

T65

2

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T2

2

T68

4

T37

2

auto[0]

auto[1]

auto[0]

auto[0]

408868

1

T5

120

T1

225

T2

9233

auto[0]

auto[1]

auto[0]

auto[1]

381360

1

T2

1278

T3

166

T111

132

auto[0]

auto[1]

auto[1]

auto[0]

375963

1

T24

657

T26

3122

T2

6714

auto[0]

auto[1]

auto[1]

auto[1]

92158

1

T26

1342

T2

1682

T3

302

auto[1]

auto[1]

auto[0]

auto[0]

190827801

1

T5

2345

T6

1446

T7

1259

auto[1]

auto[1]

auto[0]

auto[1]

63466120

1

T6

92

T23

255

T25

5269

auto[1]

auto[1]

auto[1]

auto[0]

184394322

1

T5

15

T6

44

T23

242

auto[1]

auto[1]

auto[1]

auto[1]

15388675

1

T6

56

T23

209

T24

970

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1157444

1

T5

56

T6

2

T7

2

auto[1]

454187848

1

T5

2426

T6

1638

T7

1273

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

390097028

1

T5

2482

T6

125

T7

1268

auto[1]

65248264

1

T6

1515

T7

7

T23

565

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10025

1

T5

2

T6

2

T7

16

auto[1]

455335267

1

T5

2480

T6

1638

T7

1259

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255092578

1

T5

2465

T6

1540

T7

1275

auto[1]

200252714

1

T5

17

T6

100

T23

451

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2366

1

T2

2

T65

2

T68

2

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T2

2

T68

2

T158

2

auto[0]

auto[1]

auto[0]

auto[0]

352541

1

T5

54

T26

675

T1

113

auto[0]

auto[1]

auto[0]

auto[1]

362815

1

T2

1111

T3

317

T111

44

auto[0]

auto[1]

auto[1]

auto[0]

348403

1

T24

2633

T26

2142

T2

6331

auto[0]

auto[1]

auto[1]

auto[1]

86851

1

T24

652

T26

659

T2

2115

auto[1]

auto[1]

auto[0]

auto[0]

196174465

1

T5

2411

T6

79

T7

1257

auto[1]

auto[1]

auto[0]

auto[1]

58194328

1

T6

1459

T7

2

T23

352

auto[1]

auto[1]

auto[1]

auto[0]

193215644

1

T5

15

T6

44

T23

238

auto[1]

auto[1]

auto[1]

auto[1]

6600220

1

T6

56

T23

213

T24

318

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded