Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	800539080	75349	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	800539080	75349	0	0
T1	71725	44	0	0
T2	2238645	3115	0	0
T3	256015	114	0	0
T10	101400	89	0	0
T11	0	392	0	0
T12	0	69	0	0
T13	0	624	0	0
T14	0	505	0	0
T15	0	189	0	0
T16	0	186	0	0
T17	12805	0	0	0
T18	5640	0	0	0
T19	4115	0	0	0
T20	595225	0	0	0
T21	10995	0	0	0
T22	5130	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	160107816	11127	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	11127	0	0
T1	14345	7	0	0
T2	447729	446	0	0
T3	51203	19	0	0
T10	20280	14	0	0
T11	0	50	0	0
T12	0	9	0	0
T13	0	109	0	0
T14	0	80	0	0
T15	0	26	0	0
T16	0	27	0	0
T17	2561	0	0	0
T18	1128	0	0	0
T19	823	0	0	0
T20	119045	0	0	0
T21	2199	0	0	0
T22	1026	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	160107816	15150	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	15150	0	0
T1	14345	9	0	0
T2	447729	622	0	0
T3	51203	24	0	0
T10	20280	18	0	0
T11	0	78	0	0
T12	0	14	0	0
T13	0	126	0	0
T14	0	103	0	0
T15	0	37	0	0
T16	0	38	0	0
T17	2561	0	0	0
T18	1128	0	0	0
T19	823	0	0	0
T20	119045	0	0	0
T21	2199	0	0	0
T22	1026	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	160107816	23155	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	23155	0	0
T1	14345	12	0	0
T2	447729	975	0	0
T3	51203	30	0	0
T10	20280	25	0	0
T11	0	134	0	0
T12	0	22	0	0
T13	0	155	0	0
T14	0	140	0	0
T15	0	57	0	0
T16	0	62	0	0
T17	2561	0	0	0
T18	1128	0	0	0
T19	823	0	0	0
T20	119045	0	0	0
T21	2199	0	0	0
T22	1026	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	160107816	10784	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	10784	0	0
T1	14345	7	0	0
T2	447729	444	0	0
T3	51203	19	0	0
T10	20280	14	0	0
T11	0	50	0	0
T12	0	10	0	0
T13	0	109	0	0
T14	0	80	0	0
T15	0	26	0	0
T16	0	23	0	0
T17	2561	0	0	0
T18	1128	0	0	0
T19	823	0	0	0
T20	119045	0	0	0
T21	2199	0	0	0
T22	1026	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	160107816	15133	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	15133	0	0
T1	14345	9	0	0
T2	447729	628	0	0
T3	51203	22	0	0
T10	20280	18	0	0
T11	0	80	0	0
T12	0	14	0	0
T13	0	125	0	0
T14	0	102	0	0
T15	0	43	0	0
T16	0	36	0	0
T17	2561	0	0	0
T18	1128	0	0	0
T19	823	0	0	0
T20	119045	0	0	0
T21	2199	0	0	0
T22	1026	0	0	0