Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T25,T4,T1

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	160107816	157063245	0	0
AllClkBypReqTrue_A	160107816	125468	0	0
IoClkBypReqFalse_A	160107816	156983685	0	2415
IoClkBypReqTrue_A	160107816	200174	0	0
LcClkBypAckFalse_A	160107816	157072387	0	0
LcClkBypAckTrue_A	160107816	116326	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	157063245	0	0
T1	14345	13900	0	0
T4	27538	2016	0	0
T5	2655	2407	0	0
T6	1723	1536	0	0
T7	1551	1361	0	0
T23	2347	2070	0	0
T24	1126	1120	0	0
T25	3198	2766	0	0
T26	1826	1812	0	0
T27	1441	1321	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	125468	0	0
T1	14345	285	0	0
T2	447729	2543	0	0
T4	27538	0	0	0
T6	1723	37	0	0
T7	1551	0	0	0
T18	0	14	0	0
T21	0	8	0	0
T22	0	19	0	0
T23	2347	98	0	0
T24	1126	0	0	0
T25	3198	354	0	0
T26	1826	0	0	0
T27	1441	7	0	0
T109	0	133	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	156983685	0	2415
T1	14345	13711	0	3
T4	27538	2000	0	3
T5	2655	2405	0	3
T6	1723	1571	0	3
T7	1551	1359	0	3
T23	2347	1846	0	3
T24	1126	1118	0	3
T25	3198	2769	0	3
T26	1826	1810	0	3
T27	1441	1326	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	200174	0	0
T1	14345	466	0	0
T2	447729	4138	0	0
T4	27538	0	0	0
T17	2561	0	0	0
T18	1128	33	0	0
T21	0	236	0	0
T23	2347	320	0	0
T24	1126	0	0	0
T25	3198	347	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T80	0	620	0	0
T82	0	60	0	0
T109	0	289	0	0
T110	0	354	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	157072387	0	0
T1	14345	13931	0	0
T4	27538	2016	0	0
T5	2655	2407	0	0
T6	1723	1573	0	0
T7	1551	1361	0	0
T23	2347	2028	0	0
T24	1126	1120	0	0
T25	3198	2882	0	0
T26	1826	1812	0	0
T27	1441	1328	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	116326	0	0
T1	14345	254	0	0
T2	447729	2439	0	0
T4	27538	0	0	0
T17	2561	0	0	0
T18	1128	30	0	0
T21	0	77	0	0
T23	2347	140	0	0
T24	1126	0	0	0
T25	3198	238	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T80	0	353	0	0
T82	0	30	0	0
T109	0	131	0	0
T110	0	250	0	0