Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1834040136	16264	0	0
TransStop_A	1834040136	8339	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1834040136	16264	0	0
T1	239104	4	0	0
T2	0	387	0	0
T3	0	39	0	0
T4	224792	0	0	0
T5	10952	4	0	0
T6	7184	0	0	0
T7	5892	0	0	0
T17	0	4	0	0
T23	12692	0	0	0
T24	64328	13	0	0
T25	39988	0	0	0
T26	91364	23	0	0
T27	5768	0	0	0
T81	0	4	0	0
T111	0	15	0	0
T112	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1834040136	8339	0	0
T1	239104	4	0	0
T2	0	206	0	0
T3	0	10	0	0
T4	224792	0	0	0
T5	10952	4	0	0
T6	7184	0	0	0
T7	5892	0	0	0
T11	0	9	0	0
T17	0	4	0	0
T23	12692	0	0	0
T24	64328	1	0	0
T25	39988	0	0	0
T26	91364	3	0	0
T27	5768	0	0	0
T81	0	4	0	0
T85	0	1	0	0
T111	0	9	0	0
T112	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	458510034	4115	0	0
TransStop_A	458510034	2121	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458510034	4115	0	0
T1	59776	1	0	0
T2	0	100	0	0
T3	0	9	0	0
T4	56198	0	0	0
T5	2738	1	0	0
T6	1796	0	0	0
T7	1473	0	0	0
T17	0	1	0	0
T23	3173	0	0	0
T24	16082	3	0	0
T25	9997	0	0	0
T26	22841	5	0	0
T27	1442	0	0	0
T81	0	1	0	0
T111	0	5	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458510034	2121	0	0
T1	59776	1	0	0
T2	0	50	0	0
T3	0	4	0	0
T4	56198	0	0	0
T5	2738	1	0	0
T6	1796	0	0	0
T7	1473	0	0	0
T17	0	1	0	0
T23	3173	0	0	0
T24	16082	1	0	0
T25	9997	0	0	0
T26	22841	1	0	0
T27	1442	0	0	0
T81	0	1	0	0
T111	0	3	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	458510034	4008	0	0
TransStop_A	458510034	2049	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458510034	4008	0	0
T1	59776	1	0	0
T2	0	98	0	0
T3	0	10	0	0
T4	56198	0	0	0
T5	2738	1	0	0
T6	1796	0	0	0
T7	1473	0	0	0
T17	0	1	0	0
T23	3173	0	0	0
T24	16082	4	0	0
T25	9997	0	0	0
T26	22841	7	0	0
T27	1442	0	0	0
T81	0	1	0	0
T111	0	4	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458510034	2049	0	0
T1	59776	1	0	0
T2	0	54	0	0
T3	0	2	0	0
T4	56198	0	0	0
T5	2738	1	0	0
T6	1796	0	0	0
T7	1473	0	0	0
T11	0	3	0	0
T17	0	1	0	0
T23	3173	0	0	0
T24	16082	0	0	0
T25	9997	0	0	0
T26	22841	1	0	0
T27	1442	0	0	0
T81	0	1	0	0
T111	0	2	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	458510034	4078	0	0
TransStop_A	458510034	2106	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458510034	4078	0	0
T1	59776	1	0	0
T2	0	97	0	0
T3	0	6	0	0
T4	56198	0	0	0
T5	2738	1	0	0
T6	1796	0	0	0
T7	1473	0	0	0
T17	0	1	0	0
T23	3173	0	0	0
T24	16082	1	0	0
T25	9997	0	0	0
T26	22841	6	0	0
T27	1442	0	0	0
T81	0	1	0	0
T111	0	4	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458510034	2106	0	0
T1	59776	1	0	0
T2	0	54	0	0
T3	0	1	0	0
T4	56198	0	0	0
T5	2738	1	0	0
T6	1796	0	0	0
T7	1473	0	0	0
T11	0	3	0	0
T17	0	1	0	0
T23	3173	0	0	0
T24	16082	0	0	0
T25	9997	0	0	0
T26	22841	0	0	0
T27	1442	0	0	0
T81	0	1	0	0
T85	0	1	0	0
T111	0	3	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	458510034	4063	0	0
TransStop_A	458510034	2063	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458510034	4063	0	0
T1	59776	1	0	0
T2	0	92	0	0
T3	0	14	0	0
T4	56198	0	0	0
T5	2738	1	0	0
T6	1796	0	0	0
T7	1473	0	0	0
T17	0	1	0	0
T23	3173	0	0	0
T24	16082	5	0	0
T25	9997	0	0	0
T26	22841	5	0	0
T27	1442	0	0	0
T81	0	1	0	0
T111	0	2	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458510034	2063	0	0
T1	59776	1	0	0
T2	0	48	0	0
T3	0	3	0	0
T4	56198	0	0	0
T5	2738	1	0	0
T6	1796	0	0	0
T7	1473	0	0	0
T11	0	3	0	0
T17	0	1	0	0
T23	3173	0	0	0
T24	16082	0	0	0
T25	9997	0	0	0
T26	22841	1	0	0
T27	1442	0	0	0
T81	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0