Module Definition
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Module : clkmgr_lost_calib_regwen_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if 100.00 100.00



Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RegwenOff_A 160107816 22129863 0 63


RegwenOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160107816 22129863 0 63
T1 14345 3676 0 0
T2 447729 316036 0 0
T3 51203 8856 0 1
T10 20280 6625 0 1
T11 0 48196 0 0
T12 0 6313 0 1
T13 0 939011 0 0
T14 0 775745 0 0
T15 0 18343 0 1
T16 0 24195 0 1
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 0 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T28 0 0 0 1
T29 0 0 0 1
T33 0 0 0 1
T113 0 0 0 1
T114 0 0 0 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%