Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	160107816	22129863	0	63

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	22129863	0	63
T1	14345	3676	0	0
T2	447729	316036	0	0
T3	51203	8856	0	1
T10	20280	6625	0	1
T11	0	48196	0	0
T12	0	6313	0	1
T13	0	939011	0	0
T14	0	775745	0	0
T15	0	18343	0	1
T16	0	24195	0	1
T17	2561	0	0	0
T18	1128	0	0	0
T19	823	0	0	0
T20	119045	0	0	0
T21	2199	0	0	0
T22	1026	0	0	0
T28	0	0	0	1
T29	0	0	0	1
T33	0	0	0	1
T113	0	0	0	1
T114	0	0	0	1