Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div2_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div4_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_main_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_usb_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_div2_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_div2_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_div4_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_div4_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_main_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_main_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_usb_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_usb_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 955541 0 0
SrcPulseCheck_M 2147483647 952637 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 955541 0 0
T1 233864 92 0 0
T2 3488460 11960 0 0
T3 1031714 586 0 0
T4 58412 70 0 0
T10 217313 174 0 0
T11 0 1304 0 0
T12 0 468 0 0
T13 0 4203 0 0
T14 0 3086 0 0
T17 11959 0 0 0
T18 18399 0 0 0
T19 12297 0 0 0
T20 477145 190 0 0
T21 10320 0 0 0
T22 17338 0 0 0
T30 0 144 0 0
T31 0 180 0 0
T32 0 170 0 0
T55 10110 3 0 0
T56 3066 2 0 0
T57 3354 2 0 0
T59 8141 0 0 0
T60 10490 1 0 0
T63 8415 1 0 0
T71 0 474 0 0
T115 10573 1 0 0
T116 5679 1 0 0
T117 4589 0 0 0
T118 5412 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 952637 0 0
T1 62160 92 0 0
T2 2349823 11321 0 0
T3 239994 586 0 0
T4 70513 70 0 0
T10 744 174 0 0
T11 0 1304 0 0
T12 0 468 0 0
T13 0 4203 0 0
T14 0 3086 0 0
T17 7065 0 0 0
T18 5873 0 0 0
T19 4084 0 0 0
T20 272024 190 0 0
T21 6095 0 0 0
T22 5464 0 0 0
T30 0 144 0 0
T31 0 180 0 0
T32 0 170 0 0
T55 4048 3 0 0
T56 24179 2 0 0
T57 2834 2 0 0
T59 3343 0 0 0
T60 20095 1 0 0
T63 3701 1 0 0
T71 0 474 0 0
T115 4162 1 0 0
T116 10852 1 0 0
T117 23876 0 0 0
T118 5145 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 431080814 25573 0 0
SrcPulseCheck_M 160964563 25573 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431080814 25573 0 0
T1 57383 8 0 0
T2 796685 671 0 0
T3 258706 40 0 0
T4 53949 14 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2534 0 0 0
T18 4515 0 0 0
T19 3115 0 0 0
T20 119045 38 0 0
T21 2132 0 0 0
T22 4280 0 0 0
T30 0 28 0 0
T31 0 36 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 25573 0 0
T1 14345 8 0 0
T2 447729 671 0 0
T3 51203 40 0 0
T4 27538 14 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 38 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 28 0 0
T31 0 36 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 431080814 31062 0 0
SrcPulseCheck_M 160964563 31083 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431080814 31062 0 0
T1 57383 8 0 0
T2 796685 681 0 0
T3 258706 40 0 0
T4 53949 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2534 0 0 0
T18 4515 0 0 0
T19 3115 0 0 0
T20 119045 76 0 0
T21 2132 0 0 0
T22 4280 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 31083 0 0
T1 14345 8 0 0
T2 447729 681 0 0
T3 51203 40 0 0
T4 27538 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 76 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 31053 0 0
SrcPulseCheck_M 431080814 31065 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 31053 0 0
T1 14345 8 0 0
T2 447729 681 0 0
T3 51203 40 0 0
T4 27538 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 76 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 431080814 31065 0 0
T1 57383 8 0 0
T2 796685 681 0 0
T3 258706 40 0 0
T4 53949 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2534 0 0 0
T18 4515 0 0 0
T19 3115 0 0 0
T20 119045 76 0 0
T21 2132 0 0 0
T22 4280 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 215531632 25573 0 0
SrcPulseCheck_M 160964563 25573 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 215531632 25573 0 0
T1 29246 8 0 0
T2 397891 671 0 0
T3 129232 40 0 0
T4 15437 14 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 1207 0 0 0
T18 2301 0 0 0
T19 1518 0 0 0
T20 32870 38 0 0
T21 1077 0 0 0
T22 2164 0 0 0
T30 0 28 0 0
T31 0 36 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 25573 0 0
T1 14345 8 0 0
T2 447729 671 0 0
T3 51203 40 0 0
T4 27538 14 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 38 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 28 0 0
T31 0 36 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 215531632 31107 0 0
SrcPulseCheck_M 160964563 31121 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 215531632 31107 0 0
T1 29246 8 0 0
T2 397891 681 0 0
T3 129232 40 0 0
T4 15437 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 1207 0 0 0
T18 2301 0 0 0
T19 1518 0 0 0
T20 32870 76 0 0
T21 1077 0 0 0
T22 2164 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 31121 0 0
T1 14345 8 0 0
T2 447729 681 0 0
T3 51203 40 0 0
T4 27538 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 76 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 31098 0 0
SrcPulseCheck_M 215531632 31110 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 31098 0 0
T1 14345 8 0 0
T2 447729 681 0 0
T3 51203 40 0 0
T4 27538 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 76 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 215531632 31110 0 0
T1 29246 8 0 0
T2 397891 681 0 0
T3 129232 40 0 0
T4 15437 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 1207 0 0 0
T18 2301 0 0 0
T19 1518 0 0 0
T20 32870 76 0 0
T21 1077 0 0 0
T22 2164 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 107765282 25573 0 0
SrcPulseCheck_M 160964563 25573 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 107765282 25573 0 0
T1 14622 8 0 0
T2 198945 671 0 0
T3 64615 40 0 0
T4 7719 14 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 603 0 0 0
T18 1151 0 0 0
T19 759 0 0 0
T20 16436 38 0 0
T21 538 0 0 0
T22 1082 0 0 0
T30 0 28 0 0
T31 0 36 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 25573 0 0
T1 14345 8 0 0
T2 447729 671 0 0
T3 51203 40 0 0
T4 27538 14 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 38 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 28 0 0
T31 0 36 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 107765282 31009 0 0
SrcPulseCheck_M 160964563 31038 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 107765282 31009 0 0
T1 14622 8 0 0
T2 198945 681 0 0
T3 64615 40 0 0
T4 7719 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 603 0 0 0
T18 1151 0 0 0
T19 759 0 0 0
T20 16436 76 0 0
T21 538 0 0 0
T22 1082 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 31038 0 0
T1 14345 8 0 0
T2 447729 681 0 0
T3 51203 40 0 0
T4 27538 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 76 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 31008 0 0
SrcPulseCheck_M 107765282 31014 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 31008 0 0
T1 14345 8 0 0
T2 447729 681 0 0
T3 51203 40 0 0
T4 27538 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 76 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 107765282 31014 0 0
T1 14622 8 0 0
T2 198945 681 0 0
T3 64615 40 0 0
T4 7719 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 603 0 0 0
T18 1151 0 0 0
T19 759 0 0 0
T20 16436 76 0 0
T21 538 0 0 0
T22 1082 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 460613084 25573 0 0
SrcPulseCheck_M 160964563 25573 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460613084 25573 0 0
T1 59776 8 0 0
T2 851428 671 0 0
T3 269494 40 0 0
T4 56198 14 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2640 0 0 0
T18 4702 0 0 0
T19 3046 0 0 0
T20 124009 38 0 0
T21 2220 0 0 0
T22 4458 0 0 0
T30 0 28 0 0
T31 0 36 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 25573 0 0
T1 14345 8 0 0
T2 447729 671 0 0
T3 51203 40 0 0
T4 27538 14 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 38 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 28 0 0
T31 0 36 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 460613084 30980 0 0
SrcPulseCheck_M 160964563 30995 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 460613084 30980 0 0
T1 59776 8 0 0
T2 851428 681 0 0
T3 269494 40 0 0
T4 56198 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2640 0 0 0
T18 4702 0 0 0
T19 3046 0 0 0
T20 124009 76 0 0
T21 2220 0 0 0
T22 4458 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 30995 0 0
T1 14345 8 0 0
T2 447729 681 0 0
T3 51203 40 0 0
T4 27538 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 76 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 30976 0 0
SrcPulseCheck_M 460613084 30981 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 30976 0 0
T1 14345 8 0 0
T2 447729 681 0 0
T3 51203 40 0 0
T4 27538 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 76 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 460613084 30981 0 0
T1 59776 8 0 0
T2 851428 681 0 0
T3 269494 40 0 0
T4 56198 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2640 0 0 0
T18 4702 0 0 0
T19 3046 0 0 0
T20 124009 76 0 0
T21 2220 0 0 0
T22 4458 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT1,T2,T20
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 220952677 25095 0 0
SrcPulseCheck_M 160964563 25573 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220952677 25095 0 0
T1 28693 8 0 0
T2 406387 671 0 0
T3 129359 40 0 0
T4 26975 7 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 1266 0 0 0
T18 2257 0 0 0
T19 1512 0 0 0
T20 59525 23 0 0
T21 1066 0 0 0
T22 2140 0 0 0
T30 0 26 0 0
T31 0 18 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 25573 0 0
T1 14345 8 0 0
T2 447729 671 0 0
T3 51203 40 0 0
T4 27538 14 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 38 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 28 0 0
T31 0 36 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 220952677 30983 0 0
SrcPulseCheck_M 160964563 31163 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220952677 30983 0 0
T1 28693 8 0 0
T2 406387 681 0 0
T3 129359 40 0 0
T4 26975 21 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 1266 0 0 0
T18 2257 0 0 0
T19 1512 0 0 0
T20 59525 73 0 0
T21 1066 0 0 0
T22 2140 0 0 0
T30 0 56 0 0
T31 0 69 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 31163 0 0
T1 14345 8 0 0
T2 447729 681 0 0
T3 51203 40 0 0
T4 27538 28 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 76 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 56 0 0
T31 0 72 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 30856 0 0
SrcPulseCheck_M 220952677 31036 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 30856 0 0
T1 14345 8 0 0
T2 447729 681 0 0
T3 51203 40 0 0
T4 27538 21 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 2561 0 0 0
T18 1128 0 0 0
T19 823 0 0 0
T20 119045 73 0 0
T21 2199 0 0 0
T22 1026 0 0 0
T30 0 55 0 0
T31 0 65 0 0
T32 0 6 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 220952677 31036 0 0
T1 28693 8 0 0
T2 406387 681 0 0
T3 129359 40 0 0
T4 26975 25 0 0
T10 0 14 0 0
T11 0 64 0 0
T17 1266 0 0 0
T18 2257 0 0 0
T19 1512 0 0 0
T20 59525 75 0 0
T21 1066 0 0 0
T22 2140 0 0 0
T30 0 56 0 0
T31 0 71 0 0
T32 0 6 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T56,T60
10CoveredT58,T56,T60
11CoveredT115,T119,T120

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T56,T60
10CoveredT115,T119,T120
11CoveredT58,T56,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 34 0 0
SrcPulseCheck_M 431080814 34 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 34 0 0
T56 3066 1 0 0
T58 3540 1 0 0
T60 10490 1 0 0
T64 6112 1 0 0
T115 10573 2 0 0
T117 4589 1 0 0
T119 2628 2 0 0
T121 3694 1 0 0
T122 6196 1 0 0
T123 9692 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 431080814 34 0 0
T56 49064 1 0 0
T58 14776 1 0 0
T60 41960 1 0 0
T64 58673 1 0 0
T115 10150 2 0 0
T117 48961 1 0 0
T119 9703 2 0 0
T121 7237 1 0 0
T122 5947 1 0 0
T123 9592 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T56,T60
10CoveredT58,T56,T60
11CoveredT60,T117,T119

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T56,T60
10CoveredT60,T117,T119
11CoveredT58,T56,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 32 0 0
SrcPulseCheck_M 431080814 32 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 32 0 0
T56 3066 1 0 0
T58 3540 1 0 0
T60 10490 2 0 0
T64 6112 1 0 0
T117 4589 2 0 0
T119 2628 2 0 0
T120 5918 3 0 0
T121 3694 1 0 0
T123 9692 2 0 0
T124 4378 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 431080814 32 0 0
T56 49064 1 0 0
T58 14776 1 0 0
T60 41960 2 0 0
T64 58673 1 0 0
T117 48961 2 0 0
T119 9703 2 0 0
T120 5918 3 0 0
T121 7237 1 0 0
T123 9592 2 0 0
T124 9136 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT55,T56,T60
10CoveredT55,T56,T60
11CoveredT55,T56,T124

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT55,T56,T60
10CoveredT55,T56,T124
11CoveredT55,T56,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 36 0 0
SrcPulseCheck_M 215531632 36 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 36 0 0
T55 10110 3 0 0
T56 3066 2 0 0
T57 3354 2 0 0
T59 8141 1 0 0
T60 10490 1 0 0
T63 8415 1 0 0
T115 10573 1 0 0
T116 5679 1 0 0
T117 4589 3 0 0
T118 5412 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 215531632 36 0 0
T55 4048 3 0 0
T56 24179 2 0 0
T57 2834 2 0 0
T59 3343 1 0 0
T60 20095 1 0 0
T63 3701 1 0 0
T115 4162 1 0 0
T116 10852 1 0 0
T117 23876 3 0 0
T118 5145 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT55,T56,T60
10CoveredT55,T56,T60
11CoveredT55,T56,T125

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT55,T56,T60
10CoveredT55,T56,T125
11CoveredT55,T56,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 31 0 0
SrcPulseCheck_M 215531632 31 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 31 0 0
T55 10110 3 0 0
T56 3066 2 0 0
T57 3354 2 0 0
T59 8141 1 0 0
T60 10490 1 0 0
T63 8415 1 0 0
T115 10573 2 0 0
T116 5679 1 0 0
T117 4589 3 0 0
T126 4521 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 215531632 31 0 0
T55 4048 3 0 0
T56 24179 2 0 0
T57 2834 2 0 0
T59 3343 1 0 0
T60 20095 1 0 0
T63 3701 1 0 0
T115 4162 2 0 0
T116 10852 1 0 0
T117 23876 3 0 0
T126 4108 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T55,T57
10CoveredT58,T55,T57
11CoveredT63,T117,T119

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T55,T57
10CoveredT63,T117,T119
11CoveredT58,T55,T57

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 32 0 0
SrcPulseCheck_M 107765282 32 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 32 0 0
T55 10110 1 0 0
T57 3354 1 0 0
T58 3540 1 0 0
T61 3661 1 0 0
T63 8415 3 0 0
T64 6112 1 0 0
T117 4589 3 0 0
T119 2628 2 0 0
T123 9692 1 0 0
T127 6605 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 107765282 32 0 0
T55 2025 1 0 0
T57 1416 1 0 0
T58 3471 1 0 0
T61 3405 1 0 0
T63 1850 3 0 0
T64 14430 1 0 0
T117 11936 3 0 0
T119 2226 2 0 0
T123 2011 1 0 0
T127 6383 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T55,T63
10CoveredT58,T55,T63
11CoveredT55,T63,T117

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T55,T63
10CoveredT55,T63,T117
11CoveredT58,T55,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 38 0 0
SrcPulseCheck_M 107765282 38 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 38 0 0
T55 10110 4 0 0
T58 3540 1 0 0
T59 8141 1 0 0
T61 3661 1 0 0
T62 10394 1 0 0
T63 8415 2 0 0
T117 4589 2 0 0
T119 2628 1 0 0
T123 9692 1 0 0
T127 6605 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 107765282 38 0 0
T55 2025 4 0 0
T58 3471 1 0 0
T59 1673 1 0 0
T61 3405 1 0 0
T62 4560 1 0 0
T63 1850 2 0 0
T117 11936 2 0 0
T119 2226 1 0 0
T123 2011 1 0 0
T127 6383 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T56,T57
10CoveredT58,T56,T57
11CoveredT56,T57,T119

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T56,T57
10CoveredT56,T57,T119
11CoveredT58,T56,T57

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 22 0 0
SrcPulseCheck_M 460613084 22 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 22 0 0
T56 3066 4 0 0
T57 3354 2 0 0
T58 3540 1 0 0
T61 3661 1 0 0
T62 10394 1 0 0
T115 10573 1 0 0
T119 2628 3 0 0
T120 5918 1 0 0
T121 3694 1 0 0
T128 4636 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 460613084 22 0 0
T56 51111 4 0 0
T57 6710 2 0 0
T58 15393 1 0 0
T61 15256 1 0 0
T62 20381 1 0 0
T115 10573 1 0 0
T119 10108 3 0 0
T120 6165 1 0 0
T121 7539 1 0 0
T128 9461 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T56,T57
10CoveredT58,T56,T57
11CoveredT56

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT58,T56,T57
10CoveredT56
11CoveredT58,T56,T57

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 19 0 0
SrcPulseCheck_M 460613084 19 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 19 0 0
T56 3066 4 0 0
T57 3354 1 0 0
T58 3540 1 0 0
T115 10573 1 0 0
T120 5918 1 0 0
T121 3694 1 0 0
T125 3922 2 0 0
T128 4636 1 0 0
T129 15306 1 0 0
T130 8571 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 460613084 19 0 0
T56 51111 4 0 0
T57 6710 1 0 0
T58 15393 1 0 0
T115 10573 1 0 0
T120 6165 1 0 0
T121 7539 1 0 0
T125 11884 2 0 0
T128 9461 1 0 0
T129 15461 1 0 0
T130 8657 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT55,T60,T57
10CoveredT55,T60,T57
11CoveredT61,T128,T131

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT55,T60,T57
10CoveredT61,T128,T131
11CoveredT55,T60,T57

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 45 0 0
SrcPulseCheck_M 220952677 45 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 45 0 0
T55 10110 2 0 0
T57 3354 1 0 0
T60 10490 2 0 0
T61 3661 2 0 0
T115 10573 3 0 0
T117 4589 1 0 0
T118 5412 1 0 0
T119 2628 1 0 0
T122 6196 1 0 0
T126 4521 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 220952677 45 0 0
T55 4853 2 0 0
T57 3220 1 0 0
T60 20980 2 0 0
T61 7323 2 0 0
T115 5075 3 0 0
T117 24482 1 0 0
T118 5412 1 0 0
T119 4851 1 0 0
T122 2974 1 0 0
T126 4618 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT55,T56,T57
10CoveredT55,T56,T57
11CoveredT117,T126,T128

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT55,T56,T57
10CoveredT117,T126,T128
11CoveredT55,T56,T57

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 160964563 45 0 0
SrcPulseCheck_M 220952677 45 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 160964563 45 0 0
T55 10110 1 0 0
T56 3066 1 0 0
T57 3354 1 0 0
T61 3661 1 0 0
T115 10573 3 0 0
T116 5679 2 0 0
T117 4589 2 0 0
T118 5412 2 0 0
T119 2628 1 0 0
T126 4521 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 220952677 45 0 0
T55 4853 1 0 0
T56 24533 1 0 0
T57 3220 1 0 0
T61 7323 1 0 0
T115 5075 3 0 0
T116 11358 2 0 0
T117 24482 2 0 0
T118 5412 2 0 0
T119 4851 1 0 0
T126 4618 2 0 0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 429061536 96797 0 0
SrcPulseCheck_M 15879100 96019 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429061536 96797 0 0
T1 57383 17 0 0
T2 796685 2399 0 0
T3 258706 118 0 0
T10 77875 33 0 0
T11 0 272 0 0
T12 0 117 0 0
T13 0 1120 0 0
T14 0 760 0 0
T17 2534 0 0 0
T18 4515 0 0 0
T19 3115 0 0 0
T20 119045 0 0 0
T21 2132 0 0 0
T22 4280 0 0 0
T30 0 2 0 0
T32 0 35 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 15879100 96019 0 0
T1 1056 17 0 0
T2 263766 2184 0 0
T3 2089 118 0 0
T10 186 33 0 0
T11 0 272 0 0
T12 0 117 0 0
T13 0 1120 0 0
T14 0 760 0 0
T17 184 0 0 0
T18 329 0 0 0
T19 230 0 0 0
T20 266 0 0 0
T21 155 0 0 0
T22 312 0 0 0
T30 0 2 0 0
T32 0 35 0 0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 214562743 95850 0 0
SrcPulseCheck_M 15879100 95075 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214562743 95850 0 0
T1 29246 17 0 0
T2 397891 2385 0 0
T3 129232 119 0 0
T10 38877 33 0 0
T11 0 272 0 0
T12 0 117 0 0
T13 0 1041 0 0
T14 0 754 0 0
T17 1207 0 0 0
T18 2301 0 0 0
T19 1518 0 0 0
T20 32870 0 0 0
T21 1077 0 0 0
T22 2164 0 0 0
T30 0 2 0 0
T32 0 35 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 15879100 95075 0 0
T1 1056 17 0 0
T2 263766 2172 0 0
T3 2089 119 0 0
T10 186 33 0 0
T11 0 272 0 0
T12 0 117 0 0
T13 0 1041 0 0
T14 0 754 0 0
T17 184 0 0 0
T18 329 0 0 0
T19 230 0 0 0
T20 266 0 0 0
T21 155 0 0 0
T22 312 0 0 0
T30 0 2 0 0
T32 0 35 0 0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 107280830 94636 0 0
SrcPulseCheck_M 15879100 93869 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 107280830 94636 0 0
T1 14622 17 0 0
T2 198945 2364 0 0
T3 64615 118 0 0
T10 19439 33 0 0
T11 0 272 0 0
T12 0 117 0 0
T13 0 981 0 0
T14 0 718 0 0
T17 603 0 0 0
T18 1151 0 0 0
T19 759 0 0 0
T20 16436 0 0 0
T21 538 0 0 0
T22 1082 0 0 0
T32 0 35 0 0
T71 0 201 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 15879100 93869 0 0
T1 1056 17 0 0
T2 263766 2153 0 0
T3 2089 118 0 0
T10 186 33 0 0
T11 0 272 0 0
T12 0 117 0 0
T13 0 981 0 0
T14 0 718 0 0
T17 184 0 0 0
T18 329 0 0 0
T19 230 0 0 0
T20 266 0 0 0
T21 155 0 0 0
T22 312 0 0 0
T32 0 35 0 0
T71 0 201 0 0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 458509598 116258 0 0
SrcPulseCheck_M 15884717 115939 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 458509598 116258 0 0
T1 59776 17 0 0
T2 851428 2779 0 0
T3 269494 111 0 0
T10 81122 33 0 0
T11 0 296 0 0
T12 0 117 0 0
T13 0 1061 0 0
T14 0 854 0 0
T17 2640 0 0 0
T18 4702 0 0 0
T19 3046 0 0 0
T20 124009 0 0 0
T21 2220 0 0 0
T22 4458 0 0 0
T32 0 47 0 0
T71 0 273 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 15884717 115939 0 0
T1 1056 17 0 0
T2 265176 2779 0 0
T3 2089 111 0 0
T10 186 33 0 0
T11 0 296 0 0
T12 0 117 0 0
T13 0 1061 0 0
T14 0 854 0 0
T17 184 0 0 0
T18 329 0 0 0
T19 230 0 0 0
T20 266 0 0 0
T21 155 0 0 0
T22 312 0 0 0
T32 0 47 0 0
T71 0 273 0 0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 219943031 114147 0 0
SrcPulseCheck_M 15898835 112930 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 219943031 114147 0 0
T1 28693 17 0 0
T2 406387 2649 0 0
T3 129359 104 0 0
T10 38939 33 0 0
T11 0 296 0 0
T12 0 117 0 0
T13 0 954 0 0
T14 0 765 0 0
T17 1266 0 0 0
T18 2257 0 0 0
T19 1512 0 0 0
T20 59525 0 0 0
T21 1066 0 0 0
T22 2140 0 0 0
T32 0 35 0 0
T71 0 273 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 15898835 112930 0 0
T1 1056 17 0 0
T2 265080 2649 0 0
T3 2089 104 0 0
T10 186 33 0 0
T11 0 296 0 0
T12 0 117 0 0
T13 0 954 0 0
T14 0 765 0 0
T17 184 0 0 0
T18 329 0 0 0
T19 230 0 0 0
T20 266 0 0 0
T21 155 0 0 0
T22 312 0 0 0
T32 0 35 0 0
T71 0 273 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%