Line Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Line Coverage for Module :
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 + DW=1,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Line Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
1 |
1 |
44 |
1 |
1 |
51 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
Line Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T4,T1,T2 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T4,T1,T2 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=9,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T4,T1,T2 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T4,T1,T2 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T5,T24,T25 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T24,T25 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T24,T25 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 7 | 7 | 100.00 |
Logical | 7 | 7 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T23 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T23 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T6,T23,T25 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T20 |
1 | 0 | Covered | T4,T1,T20 |
1 | 1 | Covered | T5,T6,T7 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T23,T25 |
Cond Coverage for Module :
prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T1,T2 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T4,T1,T2 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T4,T1,T2 |
Branch Coverage for Module :
prim_subreg_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T23 |
0 |
Covered |
T5,T6,T7 |