Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	160964563	5269933	0	0
clk_enables_rd_A	160964563	53929	0	0
clk_hints_rd_A	160964563	49178	0	0
extclk_ctrl_rd_A	160964563	62105	0	0
extclk_ctrl_regwen_rd_A	160964563	47255	0	0
jitter_enable_rd_A	160964563	68225	0	0
jitter_regwen_rd_A	160964563	53810	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160964563	5269933	0	0
T2	447729	117464	0	0
T3	51203	0	0	0
T10	20280	0	0	0
T13	0	43496	0	0
T14	0	44776	0	0
T17	2561	0	0	0
T18	1128	0	0	0
T19	823	0	0	0
T20	119045	0	0	0
T21	2199	0	0	0
T22	1026	0	0	0
T30	13795	0	0	0
T37	0	131180	0	0
T65	0	73999	0	0
T66	0	52845	0	0
T67	0	102394	0	0
T68	0	149983	0	0
T69	0	27937	0	0
T70	0	128313	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160964563	53929	0	0
T2	447729	4568	0	0
T3	51203	0	0	0
T10	20280	0	0	0
T13	0	1455	0	0
T14	0	1555	0	0
T17	2561	1	0	0
T18	1128	0	0	0
T19	823	0	0	0
T20	119045	0	0	0
T21	2199	0	0	0
T22	1026	0	0	0
T29	0	2	0	0
T30	13795	0	0	0
T66	0	1837	0	0
T85	0	7	0	0
T132	0	2	0	0
T133	0	8	0	0
T134	0	6	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160964563	49178	0	0
T1	14345	0	0	0
T2	0	4163	0	0
T4	27538	0	0	0
T5	2655	7	0	0
T6	1723	0	0	0
T7	1551	0	0	0
T13	0	1493	0	0
T14	0	1321	0	0
T17	0	5	0	0
T23	2347	0	0	0
T24	1126	0	0	0
T25	3198	0	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T29	0	4	0	0
T66	0	1677	0	0
T132	0	6	0	0
T133	0	3	0	0
T135	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160964563	62105	0	0
T1	14345	0	0	0
T2	447729	4748	0	0
T4	27538	0	0	0
T13	0	1924	0	0
T14	0	1740	0	0
T17	2561	0	0	0
T18	1128	0	0	0
T20	0	104	0	0
T23	2347	38	0	0
T24	1126	0	0	0
T25	3198	48	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T80	0	75	0	0
T108	0	60	0	0
T136	0	37	0	0
T137	0	18	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160964563	47255	0	0
T2	447729	3963	0	0
T3	51203	0	0	0
T10	20280	0	0	0
T13	0	1550	0	0
T14	0	1380	0	0
T17	2561	0	0	0
T18	1128	0	0	0
T19	823	0	0	0
T20	119045	67	0	0
T21	2199	0	0	0
T22	1026	0	0	0
T30	13795	0	0	0
T37	0	4213	0	0
T66	0	1829	0	0
T108	0	35	0	0
T138	0	61	0	0
T139	0	36	0	0
T140	0	32	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160964563	68225	0	0
T1	14345	0	0	0
T2	0	5418	0	0
T4	27538	0	0	0
T5	2655	86	0	0
T6	1723	0	0	0
T7	1551	0	0	0
T13	0	1406	0	0
T14	0	2555	0	0
T17	0	134	0	0
T23	2347	0	0	0
T24	1126	0	0	0
T25	3198	0	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T29	0	380	0	0
T66	0	2263	0	0
T85	0	57	0	0
T132	0	96	0	0
T135	0	83	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160964563	53810	0	0
T2	447729	4539	0	0
T3	51203	0	0	0
T10	20280	0	0	0
T13	0	1648	0	0
T14	0	1603	0	0
T17	2561	0	0	0
T18	1128	0	0	0
T19	823	0	0	0
T20	119045	0	0	0
T21	2199	0	0	0
T22	1026	0	0	0
T30	13795	0	0	0
T37	0	5100	0	0
T66	0	1865	0	0
T141	0	2314	0	0
T142	0	2849	0	0
T143	0	2962	0	0
T144	0	2656	0	0
T145	0	2596	0	0