Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T6,T23,T25
1	1	Covered	T6,T23,T25

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	429061952	4153	0	0
g_div2.Div2Whole_A	429061952	5010	0	0
g_div4.Div4Stepped_A	214563149	4043	0	0
g_div4.Div4Whole_A	214563149	4751	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429061952	4153	0	0
T1	57384	14	0	0
T2	796685	61	0	0
T4	53949	0	0	0
T17	2534	0	0	0
T18	4515	1	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	3046	3	0	0
T24	15437	0	0	0
T25	9596	9	0	0
T26	21926	0	0	0
T27	1384	0	0	0
T80	0	14	0	0
T109	0	9	0	0
T110	0	14	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429061952	5010	0	0
T1	57384	17	0	0
T2	796685	65	0	0
T4	53949	0	0	0
T6	1724	3	0	0
T7	1495	0	0	0
T18	0	2	0	0
T21	0	7	0	0
T22	0	3	0	0
T23	3046	5	0	0
T24	15437	0	0	0
T25	9596	10	0	0
T26	21926	0	0	0
T27	1384	1	0	0
T109	0	9	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214563149	4043	0	0
T1	29247	14	0	0
T2	397891	59	0	0
T4	15437	0	0	0
T17	1207	0	0	0
T18	2302	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	1557	3	0	0
T24	7700	0	0	0
T25	5228	9	0	0
T26	10923	0	0	0
T27	656	0	0	0
T80	0	14	0	0
T109	0	9	0	0
T110	0	14	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214563149	4751	0	0
T1	29247	17	0	0
T2	397891	65	0	0
T4	15437	0	0	0
T6	848	3	0	0
T7	680	0	0	0
T18	0	2	0	0
T21	0	6	0	0
T22	0	3	0	0
T23	1557	5	0	0
T24	7700	0	0	0
T25	5228	10	0	0
T26	10923	0	0	0
T27	656	1	0	0
T109	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T6,T23,T25
1	1	Covered	T6,T23,T25

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	429061952	4153	0	0
g_div2.Div2Whole_A	429061952	5010	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429061952	4153	0	0
T1	57384	14	0	0
T2	796685	61	0	0
T4	53949	0	0	0
T17	2534	0	0	0
T18	4515	1	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	3046	3	0	0
T24	15437	0	0	0
T25	9596	9	0	0
T26	21926	0	0	0
T27	1384	0	0	0
T80	0	14	0	0
T109	0	9	0	0
T110	0	14	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429061952	5010	0	0
T1	57384	17	0	0
T2	796685	65	0	0
T4	53949	0	0	0
T6	1724	3	0	0
T7	1495	0	0	0
T18	0	2	0	0
T21	0	7	0	0
T22	0	3	0	0
T23	3046	5	0	0
T24	15437	0	0	0
T25	9596	10	0	0
T26	21926	0	0	0
T27	1384	1	0	0
T109	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T6,T23,T25
1	1	Covered	T6,T23,T25

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	214563149	4043	0	0
g_div4.Div4Whole_A	214563149	4751	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214563149	4043	0	0
T1	29247	14	0	0
T2	397891	59	0	0
T4	15437	0	0	0
T17	1207	0	0	0
T18	2302	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	1557	3	0	0
T24	7700	0	0	0
T25	5228	9	0	0
T26	10923	0	0	0
T27	656	0	0	0
T80	0	14	0	0
T109	0	9	0	0
T110	0	14	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214563149	4751	0	0
T1	29247	17	0	0
T2	397891	65	0	0
T4	15437	0	0	0
T6	848	3	0	0
T7	680	0	0	0
T18	0	2	0	0
T21	0	6	0	0
T22	0	3	0	0
T23	1557	5	0	0
T24	7700	0	0	0
T25	5228	10	0	0
T26	10923	0	0	0
T27	656	1	0	0
T109	0	9	0	0