Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	160107816	153	0	0
IoStatusRise_A	160107816	153	0	0
MainStatusFall_A	160107816	163	0	0
MainStatusRise_A	160107816	163	0	0
UsbStatusFall_A	160107816	163	0	0
UsbStatusRise_A	160107816	163	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	153	0	0
T1	14345	0	0	0
T2	447729	0	0	0
T4	27538	0	0	0
T7	1551	3	0	0
T17	2561	0	0	0
T19	0	1	0	0
T23	2347	0	0	0
T24	1126	0	0	0
T25	3198	0	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T40	0	5	0	0
T146	0	4	0	0
T147	0	3	0	0
T148	0	1	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	4	0	0
T152	0	4	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	153	0	0
T1	14345	0	0	0
T2	447729	0	0	0
T4	27538	0	0	0
T7	1551	3	0	0
T17	2561	0	0	0
T19	0	1	0	0
T23	2347	0	0	0
T24	1126	0	0	0
T25	3198	0	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T40	0	5	0	0
T146	0	4	0	0
T147	0	3	0	0
T148	0	1	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	4	0	0
T152	0	4	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	163	0	0
T1	14345	0	0	0
T2	447729	0	0	0
T4	27538	0	0	0
T7	1551	2	0	0
T17	2561	0	0	0
T19	0	2	0	0
T23	2347	0	0	0
T24	1126	0	0	0
T25	3198	0	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T40	0	2	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	1	0	0
T149	0	3	0	0
T150	0	5	0	0
T151	0	4	0	0
T152	0	5	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	163	0	0
T1	14345	0	0	0
T2	447729	0	0	0
T4	27538	0	0	0
T7	1551	2	0	0
T17	2561	0	0	0
T19	0	2	0	0
T23	2347	0	0	0
T24	1126	0	0	0
T25	3198	0	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T40	0	2	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	1	0	0
T149	0	3	0	0
T150	0	5	0	0
T151	0	4	0	0
T152	0	5	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	163	0	0
T1	14345	0	0	0
T2	447729	0	0	0
T4	27538	0	0	0
T7	1551	3	0	0
T17	2561	0	0	0
T19	0	3	0	0
T23	2347	0	0	0
T24	1126	0	0	0
T25	3198	0	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T40	0	4	0	0
T146	0	3	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	0	4	0	0
T151	0	3	0	0
T152	0	5	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160107816	163	0	0
T1	14345	0	0	0
T2	447729	0	0	0
T4	27538	0	0	0
T7	1551	3	0	0
T17	2561	0	0	0
T19	0	3	0	0
T23	2347	0	0	0
T24	1126	0	0	0
T25	3198	0	0	0
T26	1826	0	0	0
T27	1441	0	0	0
T40	0	4	0	0
T146	0	3	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	0	4	0	0
T151	0	3	0	0
T152	0	5	0	0