Line Coverage for Module :
clkmgr_cg_en_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Module :
clkmgr_cg_en_sva_if
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Module :
clkmgr_cg_en_sva_if
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
2147483647 |
51142 |
0 |
0 |
CgEnOn_A |
2147483647 |
41432 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
51142 |
0 |
0 |
T1 |
619095 |
16 |
0 |
0 |
T2 |
3494267 |
105 |
0 |
0 |
T3 |
0 |
9 |
0 |
0 |
T4 |
533811 |
24 |
0 |
0 |
T5 |
16760 |
7 |
0 |
0 |
T6 |
11035 |
3 |
0 |
0 |
T7 |
15270 |
29 |
0 |
0 |
T17 |
10830 |
1 |
0 |
0 |
T19 |
0 |
7 |
0 |
0 |
T23 |
32870 |
3 |
0 |
0 |
T24 |
165877 |
6 |
0 |
0 |
T25 |
104876 |
36 |
0 |
0 |
T26 |
235543 |
8 |
0 |
0 |
T27 |
14724 |
3 |
0 |
0 |
T40 |
0 |
25 |
0 |
0 |
T65 |
0 |
5 |
0 |
0 |
T67 |
0 |
5 |
0 |
0 |
T146 |
0 |
20 |
0 |
0 |
T147 |
0 |
15 |
0 |
0 |
T148 |
0 |
5 |
0 |
0 |
T149 |
0 |
15 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
41432 |
0 |
0 |
T1 |
619095 |
4 |
0 |
0 |
T2 |
3494267 |
440 |
0 |
0 |
T3 |
0 |
12 |
0 |
0 |
T4 |
533811 |
0 |
0 |
0 |
T5 |
16760 |
4 |
0 |
0 |
T6 |
11035 |
0 |
0 |
0 |
T7 |
15270 |
26 |
0 |
0 |
T17 |
10830 |
3 |
0 |
0 |
T19 |
0 |
10 |
0 |
0 |
T23 |
32870 |
0 |
0 |
0 |
T24 |
165877 |
3 |
0 |
0 |
T25 |
104876 |
30 |
0 |
0 |
T26 |
235543 |
5 |
0 |
0 |
T27 |
14724 |
0 |
0 |
0 |
T40 |
0 |
40 |
0 |
0 |
T65 |
0 |
4 |
0 |
0 |
T67 |
0 |
4 |
0 |
0 |
T112 |
0 |
1 |
0 |
0 |
T146 |
0 |
20 |
0 |
0 |
T147 |
0 |
15 |
0 |
0 |
T148 |
0 |
5 |
0 |
0 |
T149 |
0 |
15 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T153 |
0 |
22 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
214562743 |
163 |
0 |
0 |
CgEnOn_A |
214562743 |
163 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
214562743 |
163 |
0 |
0 |
T1 |
29246 |
0 |
0 |
0 |
T2 |
397891 |
1 |
0 |
0 |
T4 |
15437 |
0 |
0 |
0 |
T7 |
680 |
3 |
0 |
0 |
T17 |
1207 |
0 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
1556 |
0 |
0 |
0 |
T24 |
7699 |
0 |
0 |
0 |
T25 |
5228 |
0 |
0 |
0 |
T26 |
10923 |
0 |
0 |
0 |
T27 |
655 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
214562743 |
163 |
0 |
0 |
T1 |
29246 |
0 |
0 |
0 |
T2 |
397891 |
1 |
0 |
0 |
T4 |
15437 |
0 |
0 |
0 |
T7 |
680 |
3 |
0 |
0 |
T17 |
1207 |
0 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
1556 |
0 |
0 |
0 |
T24 |
7699 |
0 |
0 |
0 |
T25 |
5228 |
0 |
0 |
0 |
T26 |
10923 |
0 |
0 |
0 |
T27 |
655 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
107280830 |
163 |
0 |
0 |
CgEnOn_A |
107280830 |
163 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
107280830 |
163 |
0 |
0 |
T1 |
14622 |
0 |
0 |
0 |
T2 |
198945 |
1 |
0 |
0 |
T4 |
7719 |
0 |
0 |
0 |
T7 |
340 |
3 |
0 |
0 |
T17 |
603 |
0 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
777 |
0 |
0 |
0 |
T24 |
3850 |
0 |
0 |
0 |
T25 |
2612 |
0 |
0 |
0 |
T26 |
5461 |
0 |
0 |
0 |
T27 |
327 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
107280830 |
163 |
0 |
0 |
T1 |
14622 |
0 |
0 |
0 |
T2 |
198945 |
1 |
0 |
0 |
T4 |
7719 |
0 |
0 |
0 |
T7 |
340 |
3 |
0 |
0 |
T17 |
603 |
0 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
777 |
0 |
0 |
0 |
T24 |
3850 |
0 |
0 |
0 |
T25 |
2612 |
0 |
0 |
0 |
T26 |
5461 |
0 |
0 |
0 |
T27 |
327 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
429061536 |
163 |
0 |
0 |
CgEnOn_A |
429061536 |
156 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429061536 |
163 |
0 |
0 |
T1 |
57383 |
0 |
0 |
0 |
T2 |
796685 |
1 |
0 |
0 |
T4 |
53949 |
0 |
0 |
0 |
T7 |
1494 |
3 |
0 |
0 |
T17 |
2534 |
0 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
3045 |
0 |
0 |
0 |
T24 |
15437 |
0 |
0 |
0 |
T25 |
9596 |
0 |
0 |
0 |
T26 |
21925 |
0 |
0 |
0 |
T27 |
1384 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429061536 |
156 |
0 |
0 |
T1 |
57383 |
0 |
0 |
0 |
T2 |
796685 |
1 |
0 |
0 |
T4 |
53949 |
0 |
0 |
0 |
T7 |
1494 |
3 |
0 |
0 |
T17 |
2534 |
0 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
3045 |
0 |
0 |
0 |
T24 |
15437 |
0 |
0 |
0 |
T25 |
9596 |
0 |
0 |
0 |
T26 |
21925 |
0 |
0 |
0 |
T27 |
1384 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
458509598 |
167 |
0 |
0 |
CgEnOn_A |
458509598 |
164 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
167 |
0 |
0 |
T1 |
59776 |
0 |
0 |
0 |
T2 |
851428 |
0 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
2640 |
0 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
0 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
0 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T146 |
0 |
3 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
5 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
164 |
0 |
0 |
T1 |
59776 |
0 |
0 |
0 |
T2 |
851428 |
0 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
2640 |
0 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
0 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
0 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T146 |
0 |
3 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
107280830 |
163 |
0 |
0 |
CgEnOn_A |
107280830 |
163 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
107280830 |
163 |
0 |
0 |
T1 |
14622 |
0 |
0 |
0 |
T2 |
198945 |
1 |
0 |
0 |
T4 |
7719 |
0 |
0 |
0 |
T7 |
340 |
3 |
0 |
0 |
T17 |
603 |
0 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
777 |
0 |
0 |
0 |
T24 |
3850 |
0 |
0 |
0 |
T25 |
2612 |
0 |
0 |
0 |
T26 |
5461 |
0 |
0 |
0 |
T27 |
327 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
107280830 |
163 |
0 |
0 |
T1 |
14622 |
0 |
0 |
0 |
T2 |
198945 |
1 |
0 |
0 |
T4 |
7719 |
0 |
0 |
0 |
T7 |
340 |
3 |
0 |
0 |
T17 |
603 |
0 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
777 |
0 |
0 |
0 |
T24 |
3850 |
0 |
0 |
0 |
T25 |
2612 |
0 |
0 |
0 |
T26 |
5461 |
0 |
0 |
0 |
T27 |
327 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
458509598 |
167 |
0 |
0 |
CgEnOn_A |
458509598 |
164 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
167 |
0 |
0 |
T1 |
59776 |
0 |
0 |
0 |
T2 |
851428 |
0 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
2640 |
0 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
0 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
0 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T146 |
0 |
3 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
5 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
164 |
0 |
0 |
T1 |
59776 |
0 |
0 |
0 |
T2 |
851428 |
0 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
2640 |
0 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
0 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
0 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T146 |
0 |
3 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
107280830 |
163 |
0 |
0 |
CgEnOn_A |
107280830 |
163 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
107280830 |
163 |
0 |
0 |
T1 |
14622 |
0 |
0 |
0 |
T2 |
198945 |
1 |
0 |
0 |
T4 |
7719 |
0 |
0 |
0 |
T7 |
340 |
3 |
0 |
0 |
T17 |
603 |
0 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
777 |
0 |
0 |
0 |
T24 |
3850 |
0 |
0 |
0 |
T25 |
2612 |
0 |
0 |
0 |
T26 |
5461 |
0 |
0 |
0 |
T27 |
327 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
107280830 |
163 |
0 |
0 |
T1 |
14622 |
0 |
0 |
0 |
T2 |
198945 |
1 |
0 |
0 |
T4 |
7719 |
0 |
0 |
0 |
T7 |
340 |
3 |
0 |
0 |
T17 |
603 |
0 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
777 |
0 |
0 |
0 |
T24 |
3850 |
0 |
0 |
0 |
T25 |
2612 |
0 |
0 |
0 |
T26 |
5461 |
0 |
0 |
0 |
T27 |
327 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
3 |
0 |
0 |
T148 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T19,T40 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
214562743 |
8236 |
0 |
0 |
CgEnOn_A |
214562743 |
5819 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
214562743 |
8236 |
0 |
0 |
T1 |
29246 |
5 |
0 |
0 |
T4 |
15437 |
8 |
0 |
0 |
T5 |
1247 |
2 |
0 |
0 |
T6 |
847 |
1 |
0 |
0 |
T7 |
680 |
4 |
0 |
0 |
T23 |
1556 |
1 |
0 |
0 |
T24 |
7699 |
1 |
0 |
0 |
T25 |
5228 |
11 |
0 |
0 |
T26 |
10923 |
1 |
0 |
0 |
T27 |
655 |
1 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
214562743 |
5819 |
0 |
0 |
T1 |
29246 |
1 |
0 |
0 |
T2 |
0 |
110 |
0 |
0 |
T3 |
0 |
1 |
0 |
0 |
T4 |
15437 |
0 |
0 |
0 |
T5 |
1247 |
1 |
0 |
0 |
T6 |
847 |
0 |
0 |
0 |
T7 |
680 |
3 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
1556 |
0 |
0 |
0 |
T24 |
7699 |
0 |
0 |
0 |
T25 |
5228 |
9 |
0 |
0 |
T26 |
10923 |
0 |
0 |
0 |
T27 |
655 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T153 |
0 |
7 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T19,T40 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
107280830 |
8201 |
0 |
0 |
CgEnOn_A |
107280830 |
5784 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
107280830 |
8201 |
0 |
0 |
T1 |
14622 |
5 |
0 |
0 |
T4 |
7719 |
8 |
0 |
0 |
T5 |
623 |
2 |
0 |
0 |
T6 |
423 |
1 |
0 |
0 |
T7 |
340 |
4 |
0 |
0 |
T23 |
777 |
1 |
0 |
0 |
T24 |
3850 |
1 |
0 |
0 |
T25 |
2612 |
13 |
0 |
0 |
T26 |
5461 |
1 |
0 |
0 |
T27 |
327 |
1 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
107280830 |
5784 |
0 |
0 |
T1 |
14622 |
1 |
0 |
0 |
T2 |
0 |
111 |
0 |
0 |
T3 |
0 |
1 |
0 |
0 |
T4 |
7719 |
0 |
0 |
0 |
T5 |
623 |
1 |
0 |
0 |
T6 |
423 |
0 |
0 |
0 |
T7 |
340 |
3 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
777 |
0 |
0 |
0 |
T24 |
3850 |
0 |
0 |
0 |
T25 |
2612 |
11 |
0 |
0 |
T26 |
5461 |
0 |
0 |
0 |
T27 |
327 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T112 |
0 |
1 |
0 |
0 |
T153 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T19,T40 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
429061536 |
8306 |
0 |
0 |
CgEnOn_A |
429061536 |
5882 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429061536 |
8306 |
0 |
0 |
T1 |
57383 |
5 |
0 |
0 |
T4 |
53949 |
8 |
0 |
0 |
T5 |
2628 |
2 |
0 |
0 |
T6 |
1723 |
1 |
0 |
0 |
T7 |
1494 |
4 |
0 |
0 |
T23 |
3045 |
1 |
0 |
0 |
T24 |
15437 |
1 |
0 |
0 |
T25 |
9596 |
12 |
0 |
0 |
T26 |
21925 |
1 |
0 |
0 |
T27 |
1384 |
1 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429061536 |
5882 |
0 |
0 |
T1 |
57383 |
1 |
0 |
0 |
T2 |
0 |
114 |
0 |
0 |
T3 |
0 |
1 |
0 |
0 |
T4 |
53949 |
0 |
0 |
0 |
T5 |
2628 |
1 |
0 |
0 |
T6 |
1723 |
0 |
0 |
0 |
T7 |
1494 |
3 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T23 |
3045 |
0 |
0 |
0 |
T24 |
15437 |
0 |
0 |
0 |
T25 |
9596 |
10 |
0 |
0 |
T26 |
21925 |
0 |
0 |
0 |
T27 |
1384 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T153 |
0 |
7 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T19,T40 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
219943031 |
8318 |
0 |
0 |
CgEnOn_A |
219943031 |
5891 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
219943031 |
8318 |
0 |
0 |
T1 |
28693 |
5 |
0 |
0 |
T4 |
26975 |
8 |
0 |
0 |
T5 |
1314 |
2 |
0 |
0 |
T6 |
862 |
1 |
0 |
0 |
T7 |
724 |
4 |
0 |
0 |
T23 |
1522 |
1 |
0 |
0 |
T24 |
7719 |
1 |
0 |
0 |
T25 |
4798 |
13 |
0 |
0 |
T26 |
10963 |
1 |
0 |
0 |
T27 |
692 |
1 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
219943031 |
5891 |
0 |
0 |
T1 |
28693 |
1 |
0 |
0 |
T2 |
0 |
112 |
0 |
0 |
T3 |
0 |
1 |
0 |
0 |
T4 |
26975 |
0 |
0 |
0 |
T5 |
1314 |
1 |
0 |
0 |
T6 |
862 |
0 |
0 |
0 |
T7 |
724 |
3 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
3 |
0 |
0 |
T23 |
1522 |
0 |
0 |
0 |
T24 |
7719 |
0 |
0 |
0 |
T25 |
4798 |
11 |
0 |
0 |
T26 |
10963 |
0 |
0 |
0 |
T27 |
692 |
0 |
0 |
0 |
T40 |
0 |
4 |
0 |
0 |
T153 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Covered | T5,T24,T26 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
458509598 |
4282 |
0 |
0 |
CgEnOn_A |
458509598 |
4279 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
4282 |
0 |
0 |
T1 |
59776 |
1 |
0 |
0 |
T2 |
0 |
100 |
0 |
0 |
T3 |
0 |
9 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T5 |
2737 |
1 |
0 |
0 |
T6 |
1795 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
3 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
5 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T111 |
0 |
5 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
4279 |
0 |
0 |
T1 |
59776 |
1 |
0 |
0 |
T2 |
0 |
100 |
0 |
0 |
T3 |
0 |
9 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T5 |
2737 |
1 |
0 |
0 |
T6 |
1795 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
3 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
5 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T111 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Covered | T5,T24,T26 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
458509598 |
4175 |
0 |
0 |
CgEnOn_A |
458509598 |
4172 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
4175 |
0 |
0 |
T1 |
59776 |
1 |
0 |
0 |
T2 |
0 |
98 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T5 |
2737 |
1 |
0 |
0 |
T6 |
1795 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
4 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
7 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T111 |
0 |
4 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
4172 |
0 |
0 |
T1 |
59776 |
1 |
0 |
0 |
T2 |
0 |
98 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T5 |
2737 |
1 |
0 |
0 |
T6 |
1795 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
4 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
7 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T111 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Covered | T5,T24,T26 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
458509598 |
4245 |
0 |
0 |
CgEnOn_A |
458509598 |
4242 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
4245 |
0 |
0 |
T1 |
59776 |
1 |
0 |
0 |
T2 |
0 |
97 |
0 |
0 |
T3 |
0 |
6 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T5 |
2737 |
1 |
0 |
0 |
T6 |
1795 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
1 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
6 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T111 |
0 |
4 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
4242 |
0 |
0 |
T1 |
59776 |
1 |
0 |
0 |
T2 |
0 |
97 |
0 |
0 |
T3 |
0 |
6 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T5 |
2737 |
1 |
0 |
0 |
T6 |
1795 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
1 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
6 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T111 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 24 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
24 |
1 |
1 |
Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 24
EXPRESSION (ip_clk_en && sw_clk_en)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T25,T4 |
1 | 0 | Covered | T5,T24,T26 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
CgEnOff_A |
458509598 |
4230 |
0 |
0 |
CgEnOn_A |
458509598 |
4227 |
0 |
0 |
CgEnOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
4230 |
0 |
0 |
T1 |
59776 |
1 |
0 |
0 |
T2 |
0 |
92 |
0 |
0 |
T3 |
0 |
14 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T5 |
2737 |
1 |
0 |
0 |
T6 |
1795 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
5 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
5 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T111 |
0 |
2 |
0 |
0 |
CgEnOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458509598 |
4227 |
0 |
0 |
T1 |
59776 |
1 |
0 |
0 |
T2 |
0 |
92 |
0 |
0 |
T3 |
0 |
14 |
0 |
0 |
T4 |
56198 |
0 |
0 |
0 |
T5 |
2737 |
1 |
0 |
0 |
T6 |
1795 |
0 |
0 |
0 |
T7 |
1473 |
2 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T23 |
3173 |
0 |
0 |
0 |
T24 |
16081 |
5 |
0 |
0 |
T25 |
9997 |
0 |
0 |
0 |
T26 |
22840 |
5 |
0 |
0 |
T27 |
1441 |
0 |
0 |
0 |
T111 |
0 |
2 |
0 |
0 |