Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T25
0	1	Covered	T25,T2,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T1
1	0	Covered	T7,T19,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	970849806	14925	0	0
GateOpen_A	970849806	14925	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	970849806	14925	0	0
T1	129947	4	0	0
T2	0	294	0	0
T4	104081	0	0	0
T5	5813	4	0	0
T6	3858	0	0	0
T7	3240	12	0	0
T17	0	4	0	0
T19	0	6	0	0
T23	6904	0	0	0
T24	34706	0	0	0
T25	22234	36	0	0
T26	49275	0	0	0
T27	3060	0	0	0
T40	0	19	0	0
T112	0	4	0	0
T153	0	24	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	970849806	14925	0	0
T1	129947	4	0	0
T2	0	294	0	0
T4	104081	0	0	0
T5	5813	4	0	0
T6	3858	0	0	0
T7	3240	12	0	0
T17	0	4	0	0
T19	0	6	0	0
T23	6904	0	0	0
T24	34706	0	0	0
T25	22234	36	0	0
T26	49275	0	0	0
T27	3060	0	0	0
T40	0	19	0	0
T112	0	4	0	0
T153	0	24	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T25
0	1	Covered	T25,T2,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T1
1	0	Covered	T7,T19,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	107281238	3679	0	0
GateOpen_A	107281238	3679	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107281238	3679	0	0
T1	14623	1	0	0
T2	0	73	0	0
T4	7719	0	0	0
T5	624	1	0	0
T6	424	0	0	0
T7	340	3	0	0
T17	0	1	0	0
T19	0	1	0	0
T23	778	0	0	0
T24	3850	0	0	0
T25	2612	10	0	0
T26	5462	0	0	0
T27	328	0	0	0
T40	0	5	0	0
T112	0	1	0	0
T153	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107281238	3679	0	0
T1	14623	1	0	0
T2	0	73	0	0
T4	7719	0	0	0
T5	624	1	0	0
T6	424	0	0	0
T7	340	3	0	0
T17	0	1	0	0
T19	0	1	0	0
T23	778	0	0	0
T24	3850	0	0	0
T25	2612	10	0	0
T26	5462	0	0	0
T27	328	0	0	0
T40	0	5	0	0
T112	0	1	0	0
T153	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T25
0	1	Covered	T25,T2,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T1
1	0	Covered	T7,T19,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	214563149	3714	0	0
GateOpen_A	214563149	3714	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214563149	3714	0	0
T1	29247	1	0	0
T2	0	66	0	0
T4	15437	0	0	0
T5	1247	1	0	0
T6	848	0	0	0
T7	680	3	0	0
T17	0	1	0	0
T19	0	1	0	0
T23	1557	0	0	0
T24	7700	0	0	0
T25	5228	8	0	0
T26	10923	0	0	0
T27	656	0	0	0
T40	0	5	0	0
T112	0	1	0	0
T153	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214563149	3714	0	0
T1	29247	1	0	0
T2	0	66	0	0
T4	15437	0	0	0
T5	1247	1	0	0
T6	848	0	0	0
T7	680	3	0	0
T17	0	1	0	0
T19	0	1	0	0
T23	1557	0	0	0
T24	7700	0	0	0
T25	5228	8	0	0
T26	10923	0	0	0
T27	656	0	0	0
T40	0	5	0	0
T112	0	1	0	0
T153	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T25
0	1	Covered	T25,T2,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T1
1	0	Covered	T7,T19,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	429061952	3776	0	0
GateOpen_A	429061952	3776	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429061952	3776	0	0
T1	57384	1	0	0
T2	0	77	0	0
T4	53949	0	0	0
T5	2628	1	0	0
T6	1724	0	0	0
T7	1495	3	0	0
T17	0	1	0	0
T19	0	1	0	0
T23	3046	0	0	0
T24	15437	0	0	0
T25	9596	8	0	0
T26	21926	0	0	0
T27	1384	0	0	0
T40	0	5	0	0
T112	0	1	0	0
T153	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429061952	3776	0	0
T1	57384	1	0	0
T2	0	77	0	0
T4	53949	0	0	0
T5	2628	1	0	0
T6	1724	0	0	0
T7	1495	3	0	0
T17	0	1	0	0
T19	0	1	0	0
T23	3046	0	0	0
T24	15437	0	0	0
T25	9596	8	0	0
T26	21926	0	0	0
T27	1384	0	0	0
T40	0	5	0	0
T112	0	1	0	0
T153	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T25
0	1	Covered	T25,T2,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T1
1	0	Covered	T7,T19,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	219943467	3756	0	0
GateOpen_A	219943467	3756	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219943467	3756	0	0
T1	28693	1	0	0
T2	0	78	0	0
T4	26976	0	0	0
T5	1314	1	0	0
T6	862	0	0	0
T7	725	3	0	0
T17	0	1	0	0
T19	0	3	0	0
T23	1523	0	0	0
T24	7719	0	0	0
T25	4798	10	0	0
T26	10964	0	0	0
T27	692	0	0	0
T40	0	4	0	0
T112	0	1	0	0
T153	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219943467	3756	0	0
T1	28693	1	0	0
T2	0	78	0	0
T4	26976	0	0	0
T5	1314	1	0	0
T6	862	0	0	0
T7	725	3	0	0
T17	0	1	0	0
T19	0	3	0	0
T23	1523	0	0	0
T24	7719	0	0	0
T25	4798	10	0	0
T26	10964	0	0	0
T27	692	0	0	0
T40	0	4	0	0
T112	0	1	0	0
T153	0	6	0	0