Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	616408	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3587205

1

T5

6

T6

8

T7

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1031800	1			T5	6		T6	6		T7	12
values[0x0]	1459226	1			T5	6		T6	7		T7	9
values[0x1]	1712587	1			T5	7		T6	6		T7	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338147	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3865466

1

T5

8

T6

9

T7

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15748	1			T7	5		T1	3		T4	1
valid_sources[0x01]	15457	1			T4	1		T19	1		T11	398
valid_sources[0x02]	16274	1			T5	1		T1	2		T4	1
valid_sources[0x03]	16542	1			T1	1		T4	1		T18	1
valid_sources[0x04]	17307	1			T1	3		T19	5		T11	404
valid_sources[0x05]	15579	1			T29	1		T11	409		T8	2
valid_sources[0x06]	15576	1			T4	2		T11	413		T8	4
valid_sources[0x07]	16260	1			T1	2		T4	2		T19	2
valid_sources[0x08]	17037	1			T1	1		T4	5		T19	1
valid_sources[0x09]	14990	1			T5	1		T4	1		T19	2
valid_sources[0x0a]	15885	1			T19	5		T11	447		T8	8
valid_sources[0x0b]	15635	1			T4	3		T19	1		T11	479
valid_sources[0x0c]	17684	1			T18	1		T19	3		T11	435
valid_sources[0x0d]	17026	1			T47	1		T11	421		T8	3
valid_sources[0x0e]	16710	1			T4	2		T19	1		T20	2
valid_sources[0x0f]	15821	1			T1	1		T4	1		T19	2
valid_sources[0x10]	15858	1			T1	1		T19	2		T11	384
valid_sources[0x11]	15629	1			T1	2		T4	1		T19	4
valid_sources[0x12]	15439	1			T1	3		T19	4		T11	439
valid_sources[0x13]	14969	1			T19	2		T11	478		T8	2
valid_sources[0x14]	16058	1			T4	2		T11	447		T30	1
valid_sources[0x15]	15550	1			T4	1		T23	3		T47	1
valid_sources[0x16]	15538	1			T19	1		T11	405		T8	1
valid_sources[0x17]	15529	1			T1	1		T4	1		T19	2
valid_sources[0x18]	15015	1			T5	1		T4	3		T19	1
valid_sources[0x19]	18086	1			T11	441		T8	2		T13	343
valid_sources[0x1a]	18670	1			T4	2		T19	2		T29	2
valid_sources[0x1b]	15005	1			T1	1		T4	1		T19	4
valid_sources[0x1c]	17641	1			T1	1		T4	2		T19	3
valid_sources[0x1d]	16594	1			T4	1		T18	2		T19	4
valid_sources[0x1e]	15352	1			T1	2		T4	1		T19	3
valid_sources[0x1f]	15618	1			T4	1		T19	1		T11	416
valid_sources[0x20]	17183	1			T4	1		T3	146		T19	1
valid_sources[0x21]	15421	1			T4	2		T11	408		T8	2
valid_sources[0x22]	17339	1			T1	1		T4	1		T19	4
valid_sources[0x23]	14739	1			T1	2		T19	1		T29	1
valid_sources[0x24]	17630	1			T4	1		T19	3		T11	451
valid_sources[0x25]	19185	1			T4	2		T19	1		T11	421
valid_sources[0x26]	16853	1			T4	1		T19	2		T11	468
valid_sources[0x27]	16375	1			T1	2		T4	1		T29	2
valid_sources[0x28]	14924	1			T19	3		T11	458		T8	6
valid_sources[0x29]	16641	1			T19	1		T29	1		T11	441
valid_sources[0x2a]	15348	1			T1	1		T19	2		T11	412
valid_sources[0x2b]	15005	1			T19	1		T23	1		T11	428
valid_sources[0x2c]	16654	1			T1	2		T4	1		T19	1
valid_sources[0x2d]	16729	1			T4	2		T19	2		T29	1
valid_sources[0x2e]	16894	1			T1	2		T19	1		T11	446
valid_sources[0x2f]	17026	1			T4	2		T11	422		T12	8
valid_sources[0x30]	15456	1			T4	1		T19	3		T11	482
valid_sources[0x31]	16070	1			T1	2		T4	1		T19	3
valid_sources[0x32]	16384	1			T4	1		T18	1		T19	1
valid_sources[0x33]	17927	1			T4	4		T19	3		T11	463
valid_sources[0x34]	15380	1			T4	1		T19	1		T11	415
valid_sources[0x35]	16141	1			T5	1		T1	1		T4	5
valid_sources[0x36]	15171	1			T19	1		T11	402		T8	4
valid_sources[0x37]	15828	1			T4	1		T19	1		T11	463
valid_sources[0x38]	15772	1			T1	1		T29	1		T11	443
valid_sources[0x39]	15794	1			T1	2		T4	2		T19	1
valid_sources[0x3a]	15488	1			T11	433		T8	2		T13	485
valid_sources[0x3b]	15124	1			T1	4		T4	2		T19	2
valid_sources[0x3c]	15483	1			T1	3		T19	5		T11	482
valid_sources[0x3d]	17355	1			T4	2		T29	1		T11	453
valid_sources[0x3e]	15073	1			T4	3		T29	1		T11	450
valid_sources[0x3f]	17095	1			T4	1		T19	5		T11	378
valid_sources[0x40]	15966	1			T1	1		T4	2		T19	3
valid_sources[0x41]	17402	1			T11	456		T12	19		T13	357
valid_sources[0x42]	16062	1			T4	1		T11	446		T8	1
valid_sources[0x43]	17126	1			T19	3		T20	3		T11	470
valid_sources[0x44]	16299	1			T1	2		T4	1		T11	396
valid_sources[0x45]	15534	1			T19	2		T11	429		T8	1
valid_sources[0x46]	16372	1			T1	1		T19	1		T29	1
valid_sources[0x47]	16822	1			T11	448		T8	3		T12	3
valid_sources[0x48]	15455	1			T19	1		T11	434		T8	2
valid_sources[0x49]	16042	1			T29	1		T11	435		T8	4
valid_sources[0x4a]	15156	1			T4	1		T29	3		T11	404
valid_sources[0x4b]	14993	1			T4	4		T19	3		T29	2
valid_sources[0x4c]	16649	1			T4	2		T19	2		T11	423
valid_sources[0x4d]	17750	1			T1	1		T4	1		T19	1
valid_sources[0x4e]	16061	1			T19	3		T11	456		T8	2
valid_sources[0x4f]	15734	1			T1	2		T4	1		T18	1
valid_sources[0x50]	18090	1			T1	1		T4	1		T11	404
valid_sources[0x51]	15885	1			T19	1		T11	397		T8	2
valid_sources[0x52]	15967	1			T4	3		T19	3		T11	434
valid_sources[0x53]	16379	1			T19	6		T11	440		T8	6
valid_sources[0x54]	17365	1			T1	2		T4	5		T11	419
valid_sources[0x55]	15556	1			T7	1		T19	1		T29	1
valid_sources[0x56]	15967	1			T1	1		T4	2		T11	395
valid_sources[0x57]	16690	1			T4	2		T19	1		T11	448
valid_sources[0x58]	17109	1			T1	3		T4	1		T19	5
valid_sources[0x59]	14629	1			T4	1		T19	1		T11	427
valid_sources[0x5a]	17197	1			T1	1		T19	2		T11	439
valid_sources[0x5b]	16449	1			T4	1		T19	1		T11	424
valid_sources[0x5c]	15655	1			T4	1		T19	1		T11	403
valid_sources[0x5d]	16458	1			T1	1		T4	1		T11	473
valid_sources[0x5e]	16321	1			T1	1		T19	3		T11	426
valid_sources[0x5f]	16263	1			T5	1		T1	2		T19	4
valid_sources[0x60]	16034	1			T7	2		T1	1		T19	1
valid_sources[0x61]	16409	1			T1	1		T4	2		T19	1
valid_sources[0x62]	15143	1			T4	2		T29	1		T11	443
valid_sources[0x63]	16142	1			T19	1		T11	447		T8	3
valid_sources[0x64]	16811	1			T1	1		T4	2		T29	1
valid_sources[0x65]	16128	1			T1	1		T4	2		T19	3
valid_sources[0x66]	16233	1			T19	1		T11	441		T8	4
valid_sources[0x67]	16515	1			T5	2		T1	1		T4	1
valid_sources[0x68]	16438	1			T19	3		T29	1		T11	457
valid_sources[0x69]	16946	1			T20	7		T11	446		T8	1
valid_sources[0x6a]	16977	1			T19	2		T11	402		T8	3
valid_sources[0x6b]	18021	1			T1	4		T4	2		T29	1
valid_sources[0x6c]	16297	1			T18	1		T19	2		T11	414
valid_sources[0x6d]	16274	1			T1	2		T4	3		T19	2
valid_sources[0x6e]	15384	1			T19	2		T11	453		T8	2
valid_sources[0x6f]	20427	1			T4	1		T19	1		T29	2
valid_sources[0x70]	16464	1			T4	5		T29	2		T47	1
valid_sources[0x71]	16044	1			T4	1		T11	427		T8	6
valid_sources[0x72]	16833	1			T1	1		T4	1		T19	2
valid_sources[0x73]	15073	1			T11	405		T8	2		T12	5
valid_sources[0x74]	15537	1			T29	1		T11	474		T8	2
valid_sources[0x75]	16167	1			T20	1		T11	436		T8	1
valid_sources[0x76]	15084	1			T1	1		T4	2		T29	1
valid_sources[0x77]	16934	1			T5	1		T1	1		T4	1
valid_sources[0x78]	14886	1			T1	1		T11	448		T8	2
valid_sources[0x79]	15576	1			T4	1		T19	1		T11	437
valid_sources[0x7a]	15858	1			T7	4		T1	4		T19	2
valid_sources[0x7b]	16485	1			T1	1		T4	2		T19	1
valid_sources[0x7c]	17040	1			T6	19		T1	2		T4	1
valid_sources[0x7d]	15881	1			T4	2		T47	1		T11	433
valid_sources[0x7e]	16748	1			T7	2		T1	1		T4	3
valid_sources[0x7f]	17235	1			T4	3		T19	7		T11	404
valid_sources[0x80]	16397	1			T1	1		T29	2		T11	479

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

904459

1

T5

4

T6

4

T7

4

values[0x0]

all_enables

biggest_size

1365736

1

T5

1

T6

3

T7

2

values[0x1]

all_enables

biggest_size

1317010

1

T5

1

T6

1

T7

6