Summary for Variable csr_hint_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_hint_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1589474 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
492599391 |
1 |
|
|
T5 |
2496 |
|
T6 |
4236 |
|
T7 |
2229 |
Summary for Variable idle_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for idle_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
407479620 |
1 |
|
|
T5 |
200 |
|
T6 |
3807 |
|
T7 |
660 |
auto[1] |
86709245 |
1 |
|
|
T5 |
2298 |
|
T6 |
431 |
|
T7 |
1571 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9739 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
494179126 |
1 |
|
|
T5 |
2496 |
|
T6 |
4236 |
|
T7 |
2229 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
308646442 |
1 |
|
|
T5 |
2332 |
|
T6 |
1058 |
|
T7 |
2166 |
auto[1] |
185542423 |
1 |
|
|
T5 |
166 |
|
T6 |
3180 |
|
T7 |
65 |
Summary for Cross trans_cross
Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
10 |
0 |
10 |
100.00 |
|
Automatically Generated Cross Bins |
10 |
0 |
10 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for trans_cross
Bins
csr_hint_cp | ip_clk_en_cp | scanmode_cp | idle_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
2888 |
1 |
|
|
T29 |
200 |
|
T11 |
6 |
|
T27 |
2 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
22 |
1 |
|
|
T27 |
2 |
|
T61 |
4 |
|
T124 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
562598 |
1 |
|
|
T2 |
463 |
|
T20 |
450 |
|
T22 |
327 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
438895 |
1 |
|
|
T2 |
112 |
|
T11 |
21 |
|
T12 |
219 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
495640 |
1 |
|
|
T2 |
351 |
|
T11 |
998 |
|
T12 |
526 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
85307 |
1 |
|
|
T2 |
224 |
|
T11 |
177 |
|
T12 |
73 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
239763093 |
1 |
|
|
T5 |
179 |
|
T6 |
836 |
|
T7 |
593 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
67873673 |
1 |
|
|
T5 |
2153 |
|
T6 |
222 |
|
T7 |
1571 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
166652947 |
1 |
|
|
T5 |
19 |
|
T6 |
2969 |
|
T7 |
65 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
18306973 |
1 |
|
|
T5 |
145 |
|
T6 |
209 |
|
T2 |
809 |
User Defined Cross Bins for trans_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_idle_off |
0 |
Excluded |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_hint_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_hint_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1509733 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
492679132 |
1 |
|
|
T5 |
2496 |
|
T6 |
4236 |
|
T7 |
2229 |
Summary for Variable idle_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for idle_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
410659451 |
1 |
|
|
T5 |
384 |
|
T6 |
1073 |
|
T7 |
1876 |
auto[1] |
83529414 |
1 |
|
|
T5 |
2114 |
|
T6 |
3165 |
|
T7 |
355 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9739 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
494179126 |
1 |
|
|
T5 |
2496 |
|
T6 |
4236 |
|
T7 |
2229 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
308646442 |
1 |
|
|
T5 |
2332 |
|
T6 |
1058 |
|
T7 |
2166 |
auto[1] |
185542423 |
1 |
|
|
T5 |
166 |
|
T6 |
3180 |
|
T7 |
65 |
Summary for Cross trans_cross
Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
10 |
0 |
10 |
100.00 |
|
Automatically Generated Cross Bins |
10 |
0 |
10 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for trans_cross
Bins
csr_hint_cp | ip_clk_en_cp | scanmode_cp | idle_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
2868 |
1 |
|
|
T29 |
200 |
|
T11 |
6 |
|
T58 |
2 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
28 |
1 |
|
|
T27 |
2 |
|
T59 |
2 |
|
T60 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
492743 |
1 |
|
|
T2 |
236 |
|
T20 |
337 |
|
T22 |
239 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
462502 |
1 |
|
|
T2 |
224 |
|
T11 |
92 |
|
T12 |
74 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
460560 |
1 |
|
|
T2 |
867 |
|
T11 |
750 |
|
T12 |
336 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
86894 |
1 |
|
|
T2 |
168 |
|
T11 |
71 |
|
T12 |
74 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
243787416 |
1 |
|
|
T5 |
363 |
|
T6 |
835 |
|
T7 |
1874 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
63895598 |
1 |
|
|
T5 |
1969 |
|
T6 |
223 |
|
T7 |
290 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
165913202 |
1 |
|
|
T5 |
19 |
|
T6 |
236 |
|
T1 |
9 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
19080211 |
1 |
|
|
T5 |
145 |
|
T6 |
2942 |
|
T7 |
65 |
User Defined Cross Bins for trans_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_idle_off |
0 |
Excluded |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_hint_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_hint_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1347904 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
492840961 |
1 |
|
|
T5 |
2496 |
|
T6 |
4236 |
|
T7 |
2229 |
Summary for Variable idle_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for idle_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
429059689 |
1 |
|
|
T5 |
345 |
|
T6 |
793 |
|
T7 |
465 |
auto[1] |
65129176 |
1 |
|
|
T5 |
2153 |
|
T6 |
3445 |
|
T7 |
1766 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9739 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
494179126 |
1 |
|
|
T5 |
2496 |
|
T6 |
4236 |
|
T7 |
2229 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
308646442 |
1 |
|
|
T5 |
2332 |
|
T6 |
1058 |
|
T7 |
2166 |
auto[1] |
185542423 |
1 |
|
|
T5 |
166 |
|
T6 |
3180 |
|
T7 |
65 |
Summary for Cross trans_cross
Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
10 |
0 |
10 |
100.00 |
|
Automatically Generated Cross Bins |
10 |
0 |
10 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for trans_cross
Bins
csr_hint_cp | ip_clk_en_cp | scanmode_cp | idle_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
2886 |
1 |
|
|
T29 |
200 |
|
T11 |
10 |
|
T27 |
2 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
32 |
1 |
|
|
T27 |
4 |
|
T34 |
2 |
|
T59 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
426500 |
1 |
|
|
T2 |
407 |
|
T20 |
225 |
|
T22 |
172 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
433120 |
1 |
|
|
T2 |
168 |
|
T11 |
65 |
|
T12 |
48 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
398019 |
1 |
|
|
T2 |
637 |
|
T11 |
399 |
|
T12 |
224 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
83231 |
1 |
|
|
T2 |
168 |
|
T11 |
128 |
|
T12 |
49 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
256225164 |
1 |
|
|
T5 |
179 |
|
T6 |
764 |
|
T7 |
463 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
51553475 |
1 |
|
|
T5 |
2153 |
|
T6 |
294 |
|
T7 |
1701 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
172004599 |
1 |
|
|
T5 |
164 |
|
T6 |
27 |
|
T1 |
9 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
13055018 |
1 |
|
|
T6 |
3151 |
|
T7 |
65 |
|
T2 |
4645 |
User Defined Cross Bins for trans_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_idle_off |
0 |
Excluded |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_hint_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_hint_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1228154 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
492960711 |
1 |
|
|
T5 |
2496 |
|
T6 |
4236 |
|
T7 |
2229 |
Summary for Variable idle_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for idle_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
430889846 |
1 |
|
|
T5 |
2353 |
|
T6 |
3584 |
|
T7 |
1908 |
auto[1] |
63299019 |
1 |
|
|
T5 |
145 |
|
T6 |
654 |
|
T7 |
323 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9739 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T7 |
2 |
auto[1] |
494179126 |
1 |
|
|
T5 |
2496 |
|
T6 |
4236 |
|
T7 |
2229 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
308646442 |
1 |
|
|
T5 |
2332 |
|
T6 |
1058 |
|
T7 |
2166 |
auto[1] |
185542423 |
1 |
|
|
T5 |
166 |
|
T6 |
3180 |
|
T7 |
65 |
Summary for Cross trans_cross
Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
10 |
0 |
10 |
100.00 |
|
Automatically Generated Cross Bins |
10 |
0 |
10 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for trans_cross
Bins
csr_hint_cp | ip_clk_en_cp | scanmode_cp | idle_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
2872 |
1 |
|
|
T29 |
200 |
|
T11 |
6 |
|
T58 |
2 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
28 |
1 |
|
|
T60 |
2 |
|
T124 |
2 |
|
T172 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
354324 |
1 |
|
|
T2 |
233 |
|
T20 |
112 |
|
T22 |
76 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
424257 |
1 |
|
|
T2 |
112 |
|
T11 |
110 |
|
T12 |
122 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
355276 |
1 |
|
|
T2 |
637 |
|
T11 |
735 |
|
T12 |
165 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
87263 |
1 |
|
|
T2 |
168 |
|
T11 |
86 |
|
T12 |
24 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
256697598 |
1 |
|
|
T5 |
2332 |
|
T6 |
613 |
|
T7 |
1841 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
51162080 |
1 |
|
|
T6 |
445 |
|
T7 |
323 |
|
T2 |
2920 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
173476852 |
1 |
|
|
T5 |
19 |
|
T6 |
2969 |
|
T7 |
65 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
11621476 |
1 |
|
|
T5 |
145 |
|
T6 |
209 |
|
T2 |
508 |
User Defined Cross Bins for trans_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_idle_off |
0 |
Excluded |
ignore_enable_off |
0 |
Excluded |