Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 784074635 74402 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 784074635 74402 0 0
T1 451690 172 0 0
T2 93375 65 0 0
T3 308205 89 0 0
T4 55635 0 0 0
T11 0 1606 0 0
T12 0 598 0 0
T13 0 1006 0 0
T14 0 194 0 0
T15 0 1249 0 0
T16 0 1259 0 0
T17 0 143 0 0
T18 7930 0 0 0
T19 1121030 0 0 0
T20 5500 0 0 0
T21 7895 0 0 0
T22 9585 0 0 0
T23 7555 0 0 0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 156814927 10943 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 10943 0 0
T1 90338 22 0 0
T2 18675 9 0 0
T3 61641 12 0 0
T4 11127 0 0 0
T11 0 213 0 0
T12 0 81 0 0
T13 0 162 0 0
T14 0 31 0 0
T15 0 184 0 0
T16 0 166 0 0
T17 0 24 0 0
T18 1586 0 0 0
T19 224206 0 0 0
T20 1100 0 0 0
T21 1579 0 0 0
T22 1917 0 0 0
T23 1511 0 0 0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 156814927 14954 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 14954 0 0
T1 90338 36 0 0
T2 18675 13 0 0
T3 61641 18 0 0
T4 11127 0 0 0
T11 0 324 0 0
T12 0 123 0 0
T13 0 204 0 0
T14 0 39 0 0
T15 0 252 0 0
T16 0 256 0 0
T17 0 29 0 0
T18 1586 0 0 0
T19 224206 0 0 0
T20 1100 0 0 0
T21 1579 0 0 0
T22 1917 0 0 0
T23 1511 0 0 0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 156814927 22810 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 22810 0 0
T1 90338 56 0 0
T2 18675 21 0 0
T3 61641 30 0 0
T4 11127 0 0 0
T11 0 537 0 0
T12 0 194 0 0
T13 0 275 0 0
T14 0 54 0 0
T15 0 410 0 0
T16 0 423 0 0
T17 0 38 0 0
T18 1586 0 0 0
T19 224206 0 0 0
T20 1100 0 0 0
T21 1579 0 0 0
T22 1917 0 0 0
T23 1511 0 0 0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 156814927 10763 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 10763 0 0
T1 90338 22 0 0
T2 18675 9 0 0
T3 61641 11 0 0
T4 11127 0 0 0
T11 0 209 0 0
T12 0 77 0 0
T13 0 161 0 0
T14 0 31 0 0
T15 0 159 0 0
T16 0 161 0 0
T17 0 23 0 0
T18 1586 0 0 0
T19 224206 0 0 0
T20 1100 0 0 0
T21 1579 0 0 0
T22 1917 0 0 0
T23 1511 0 0 0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 156814927 14932 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156814927 14932 0 0
T1 90338 36 0 0
T2 18675 13 0 0
T3 61641 18 0 0
T4 11127 0 0 0
T11 0 323 0 0
T12 0 123 0 0
T13 0 204 0 0
T14 0 39 0 0
T15 0 244 0 0
T16 0 253 0 0
T17 0 29 0 0
T18 1586 0 0 0
T19 224206 0 0 0
T20 1100 0 0 0
T21 1579 0 0 0
T22 1917 0 0 0
T23 1511 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%